Searched refs:msr_base (Results 1 – 4 of 4) sorted by relevance
92 static void run_and_measure_loop(uint32_t msr_base) in run_and_measure_loop() argument94 const uint64_t branches_retired = rdmsr(msr_base + 0); in run_and_measure_loop()95 const uint64_t insn_retired = rdmsr(msr_base + 1); in run_and_measure_loop()99 pmc_results.branches_retired = rdmsr(msr_base + 0) - branches_retired; in run_and_measure_loop()440 static void masked_events_guest_test(uint32_t msr_base) in masked_events_guest_test() argument446 const uint64_t loads = rdmsr(msr_base + 0); in masked_events_guest_test()447 const uint64_t stores = rdmsr(msr_base + 1); in masked_events_guest_test()448 const uint64_t loads_stores = rdmsr(msr_base + 2); in masked_events_guest_test()457 pmc_results.loads = rdmsr(msr_base + 0) - loads; in masked_events_guest_test()458 pmc_results.stores = rdmsr(msr_base + 1) - stores; in masked_events_guest_test()[all …]
77 .msr_base = MSR_IA32_L3_CBM_BASE,91 .msr_base = MSR_IA32_L2_CBM_BASE,314 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); in mba_wrmsr_amd()339 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); in mba_wrmsr_intel()349 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); in cat_wrmsr()855 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; in rdt_init_res_defs_intel()875 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; in rdt_init_res_defs_amd()878 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; in rdt_init_res_defs_amd()
447 unsigned int msr_base; member
48 u32 msr_base; member175 hwc->config_base = pmu->msr_base + (2 * hwc->idx); in amd_uncore_add()176 hwc->event_base = pmu->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()678 pmu->msr_base = MSR_F15H_NB_PERF_CTL; in amd_uncore_df_ctx_init()809 pmu->msr_base = MSR_F16H_L2I_PERF_CTL; in amd_uncore_l3_ctx_init()943 pmu->msr_base = MSR_F19H_UMC_PERF_CTL + i * pmu->num_counters * 2; in amd_uncore_umc_ctx_init()