/linux/drivers/gpu/drm/radeon/ |
H A D | radeon_object.c | 616 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local 620 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags() 643 switch (mtaspect) { in radeon_bo_set_tiling_flags()
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H A D | evergreen_cs.c | 1182 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1185 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1191 DB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 1446 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1449 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1455 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 1474 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1477 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1483 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 2366 &bankw, &bankh, &mtaspect, in evergreen_packet3_check() [all …]
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H A D | evergreen.c | 1112 unsigned *bankh, unsigned *mtaspect, in evergreen_tiling_fields() argument 1117 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields() 1133 switch (*mtaspect) { in evergreen_tiling_fields() 1135 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; in evergreen_tiling_fields() 1136 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; in evergreen_tiling_fields() 1137 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; in evergreen_tiling_fields() 1138 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; in evergreen_tiling_fields()
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H A D | atombios_crtc.c | 1146 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local 1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base() 1334 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); in dce4_crtc_do_set_base()
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H A D | radeon.h | 356 unsigned *bankh, unsigned *mtaspect,
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_plane.c | 185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() local 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 200 tiling_info->gfx8.tile_aspect = mtaspect; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v6_0.c | 1956 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local 1960 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base() 1969 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); in dce_v6_0_crtc_do_set_base()
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H A D | dce_v8_0.c | 1925 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local 1929 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base() 1938 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); in dce_v8_0_crtc_do_set_base()
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H A D | dce_v10_0.c | 1986 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local 1990 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base() 2002 mtaspect); in dce_v10_0_crtc_do_set_base()
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H A D | dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local 2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base() 2052 mtaspect); in dce_v11_0_crtc_do_set_base()
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