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Searched refs:octeon_read_csr (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_device.c334 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); in lio_cn6xxx_enable_io_queues()
338 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_enable_io_queues()
342 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_enable_io_queues()
356 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_disable_io_queues()
362 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
377 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_disable_io_queues()
384 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_OQ); in lio_cn6xxx_disable_io_queues()
402 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT); in lio_cn6xxx_disable_io_queues()
406 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT); in lio_cn6xxx_disable_io_queues()
544 value = octeon_read_csr(oct, reg); in lio_cn6xxx_process_droq_intr_regs()
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H A Dcn23xx_pf_device.c125 CVM_CAST64(octeon_read_csr( in cn23xx_dump_pf_initialized_regs()
155 CVM_CAST64(octeon_read_csr in cn23xx_dump_pf_initialized_regs()
179 CVM_CAST64(octeon_read_csr in cn23xx_dump_pf_initialized_regs()
184 CVM_CAST64(octeon_read_csr( in cn23xx_dump_pf_initialized_regs()
494 reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_pf_setup_global_output_regs()
655 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
663 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
855 reg_val = octeon_read_csr( in cn23xx_enable_io_queues()
933 WRITE_ONCE(d32, octeon_read_csr( in cn23xx_disable_io_queues()
1148 oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff; in cn23xx_get_pcie_qlmport()
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H A Dlio_ethtool.c2928 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2931 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2935 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2938 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2946 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2949 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2956 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2963 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2967 octeon_read_csr(oct, CN6XXX_DMA_CNT(1))); in cn6xxx_read_csr_reg()
2971 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
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H A Dcn23xx_vf_device.c161 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); in cn23xx_vf_setup_global_output_regs()
166 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_vf_setup_global_output_regs()
346 reg_val = octeon_read_csr( in cn23xx_enable_vf_io_queues()
H A Docteon_droq.c840 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in octeon_enable_irq()
843 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in octeon_enable_irq()
H A Docteon_device.h746 #define octeon_read_csr(oct_dev, reg_off) \ macro
H A Docteon_device.c1012 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in octeon_set_droq_pkt_op()