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Searched refs:regUVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c611 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
615 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
642 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
663 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
748 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_5_disable_clock_gating_dpg_mode()
779 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
783 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
785 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
806 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
H A Dvcn_v4_0_3.c529 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
533 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
552 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
565 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
639 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
673 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
677 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
679 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
691 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v4_0.c676 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
680 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
707 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
728 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
813 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
844 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
848 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
850 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
871 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1248 #define regUVD_CGC_CTRL … macro
H A Dvcn_5_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_5_offset.h33 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_3_offset.h34 #define regUVD_CGC_CTRL … macro