/linux/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_reg.c | 242 reg = readl(dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down() 247 writel(reg, dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down() 268 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 273 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 277 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 283 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 287 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 293 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 297 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() 303 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down() [all …]
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/linux/drivers/gpio/ |
H A D | gpio-bcm-kona.c | 135 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set() 162 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get() 202 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_input() 226 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_output() 263 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set_debounce() 341 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_ack() 362 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_mask() 384 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_unmask() 405 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_set_type() 455 reg_base = bank->kona_gpio->reg_base; in bcm_kona_gpio_irq_handler() [all …]
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H A D | gpio-amdpt.c | 28 void __iomem *reg_base; member 41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request() 64 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free() 66 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free() 89 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe() 91 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe() 95 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe() 96 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe() 97 pt_gpio->reg_base + PT_DIRECTION_REG, NULL, in pt_gpio_probe() 118 writel(0, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_probe() [all …]
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H A D | gpio-loongson1.c | 21 void __iomem *reg_base; member 30 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), in ls1x_gpio_request() 31 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_request() 43 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), in ls1x_gpio_free() 44 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_free() 58 ls1x_gc->reg_base = devm_platform_ioremap_resource(pdev, 0); in ls1x_gpio_probe() 59 if (IS_ERR(ls1x_gc->reg_base)) in ls1x_gpio_probe() 60 return PTR_ERR(ls1x_gc->reg_base); in ls1x_gpio_probe() 62 ret = bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, in ls1x_gpio_probe() 63 ls1x_gc->reg_base + GPIO_OUTPUT, NULL, in ls1x_gpio_probe() [all …]
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H A D | gpio-loongson-64bit.c | 36 void __iomem *reg_base; member 138 void __iomem *reg_base) in loongson_gpio_init() argument 143 lgpio->reg_base = reg_base; in loongson_gpio_init() 146 lgpio->reg_base + lgpio->chip_data->in_offset, in loongson_gpio_init() 147 lgpio->reg_base + lgpio->chip_data->out_offset, in loongson_gpio_init() 149 lgpio->reg_base + lgpio->chip_data->conf_offset, in loongson_gpio_init() 177 void __iomem *reg_base; in loongson_gpio_probe() local 187 reg_base = devm_platform_ioremap_resource(pdev, 0); in loongson_gpio_probe() 188 if (IS_ERR(reg_base)) in loongson_gpio_probe() 189 return PTR_ERR(reg_base); in loongson_gpio_probe() [all …]
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/linux/arch/sh/drivers/pci/ |
H A D | pci-sh7780.c | 100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq() 140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq() 169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs() 229 tmp = __raw_readl(hose->reg_base + SH4_PCICR); in sh7780_pci66_init() 231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init() 255 chan->reg_base = 0xfe040000; in sh7780_pci_init() 262 chan->reg_base + SH4_PCICR); in sh7780_pci_init() 297 chan->reg_base + SH4_PCICR); in sh7780_pci_init() 309 chan->reg_base + SH4_PCILSR1); in sh7780_pci_init() 325 chan->reg_base + SH4_PCILSR0); in sh7780_pci_init() [all …]
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/linux/drivers/spi/ |
H A D | spi-gxp.c | 43 void __iomem *reg_base; member 53 void __iomem *reg_base = spifi->reg_base; in gxp_spi_set_mode() local 58 writeb(0x55, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode() 59 writeb(0xaa, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode() 71 void __iomem *reg_base = spifi->reg_base; in gxp_spi_read_reg() local 81 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_read_reg() 109 void __iomem *reg_base = spifi->reg_base; in gxp_spi_write_reg() local 119 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_write_reg() 158 void __iomem *reg_base = spifi->reg_base; in gxp_spi_write() local 271 if (IS_ERR(spifi->reg_base)) in gxp_spifi_probe() [all …]
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H A D | spi-fsl-spi.c | 93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local 94 __be32 __iomem *mode = ®_base->mode; in fsl_spi_change_mode() 238 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local 255 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local 260 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs() 389 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup() 427 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq() local 462 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq() local 482 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control() local 497 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe() local [all …]
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H A D | spi-cadence-quadspi.c | 442 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local 469 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext() local 491 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr() local 526 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read() local 609 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write() local 678 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup() local 709 reg = readl(reg_base + CQSPI_REG_SIZE); in cqspi_read_setup() 712 writel(reg, reg_base + CQSPI_REG_SIZE); in cqspi_read_setup() 723 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute() local 835 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable() local [all …]
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/linux/drivers/irqchip/ |
H A D | irq-csky-apb-intc.c | 34 static void __iomem *reg_base; variable 66 gc->reg_base = reg_base; in ck_set_gc() 111 reg_base = of_iomap(node, 0); in ck_intc_init_comm() 112 if (!reg_base) { in ck_intc_init_comm() 153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler() 158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler() 175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init() 176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init() 240 writel(0, reg_base + CK_INTC_NEN31_00); in ck_intc_init() 241 writel(0, reg_base + CK_INTC_NEN63_32); in ck_intc_init() [all …]
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H A D | irq-digicolor.c | 57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument 63 gc->reg_base = reg_base; in digicolor_set_gc() 74 void __iomem *reg_base; in digicolor_of_init() local 79 reg_base = of_iomap(node, 0); in digicolor_of_init() 80 if (!reg_base) { in digicolor_of_init() 86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init() 87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init() 112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init() 113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
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/linux/drivers/net/ethernet/cavium/thunder/ |
H A D | thunder_xcv.c | 47 void __iomem *reg_base; member 70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw() 72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw() 75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw() 77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw() 92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw() 95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw() 127 cfg = readq_relaxed(xcv->reg_base + XCV_CTL); in xcv_setup_link() 130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); in xcv_setup_link() 149 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_setup_link() [all …]
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/linux/drivers/ata/ |
H A D | ahci_qoriq.c | 61 struct ccsr_ahci *reg_base; member 167 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local 176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init() 177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init() 178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init() 179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init() 183 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init() 194 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init() 195 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); in ahci_qoriq_phy_init() 203 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init() [all …]
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/linux/drivers/misc/mchp_pci1xxxx/ |
H A D | mchp_pci1xxxx_gpio.c | 39 void __iomem *reg_base; member 51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction() 55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction() 106 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output() 111 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output() 207 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), in pci1xxxx_gpio_set_type() 306 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend() 308 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend() 322 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume() 398 if (!priv->reg_base) in pci1xxxx_gpio_probe() [all …]
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/linux/drivers/remoteproc/ |
H A D | qcom_q6v5_wcss.c | 110 void __iomem *reg_base; member 161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset() 163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset() 166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset() 168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset() 344 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on() 346 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on() 421 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on() 423 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on() 545 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown() [all …]
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H A D | mtk_scp.c | 161 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert() 163 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert() 170 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert() 172 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert() 207 scp->cluster->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler() 224 scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); in mt8192_scp_irq_handler() 227 writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); in mt8192_scp_irq_handler() 413 scp->cluster->reg_base + MT8183_SCP_CACHE_CON); in mt8183_scp_before_load() 460 scp->cluster->reg_base + MT8183_SCP_CACHE_CON); in mt8186_scp_before_load() 709 writel(0, scp->cluster->reg_base + MT8183_WDT_CFG); in mt8183_scp_stop() [all …]
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/linux/drivers/video/fbdev/mmp/hw/ |
H A D | mmp_spi.c | 34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local 55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write() 58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write() 60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write() 63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write() 71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write() 74 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write() 83 void __iomem *reg_base = (void __iomem *) in lcd_spi_setup() local 91 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_setup() 102 reg_base + SPU_IOPAD_CONTROL); in lcd_spi_setup() [all …]
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/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
H A D | ptp.c | 160 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec() 164 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec() 174 return readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_nsec() 259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update() 261 ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_atomic_update() 269 regval = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update() 272 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update() 354 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine() 391 writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_start() 438 *clk = readq(ptp->reg_base + PTP_TIMESTAMP); in ptp_get_tstmp() [all …]
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/linux/drivers/clk/samsung/ |
H A D | clk-s5pv210-audss.c | 24 static void __iomem *reg_base; variable 73 if (IS_ERR(reg_base)) in s5pv210_audss_clk_probe() 74 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe() 116 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe() 138 reg_base + ASS_CLK_GATE, 6, 0, &lock); in s5pv210_audss_clk_probe() 144 reg_base + ASS_CLK_GATE, 5, 0, &lock); in s5pv210_audss_clk_probe() 147 reg_base + ASS_CLK_GATE, 4, 0, &lock); in s5pv210_audss_clk_probe() 150 reg_base + ASS_CLK_GATE, 3, 0, &lock); in s5pv210_audss_clk_probe() 153 reg_base + ASS_CLK_GATE, 2, 0, &lock); in s5pv210_audss_clk_probe() 156 reg_base + ASS_CLK_GATE, 1, 0, &lock); in s5pv210_audss_clk_probe() [all …]
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H A D | clk-exynos-audss.c | 21 static void __iomem *reg_base; variable 139 if (IS_ERR(reg_base)) in exynos_audss_clk_probe() 140 return PTR_ERR(reg_base); in exynos_audss_clk_probe() 186 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe() 197 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe() 213 reg_base + ASS_CLK_GATE, 0, 0, &lock); in exynos_audss_clk_probe() 217 reg_base + ASS_CLK_GATE, 2, 0, &lock); in exynos_audss_clk_probe() 221 reg_base + ASS_CLK_GATE, 3, 0, &lock); in exynos_audss_clk_probe() 225 reg_base + ASS_CLK_GATE, 4, 0, &lock); in exynos_audss_clk_probe() 232 reg_base + ASS_CLK_GATE, 5, 0, &lock); in exynos_audss_clk_probe() [all …]
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/linux/drivers/rtc/ |
H A D | rtc-zynqmp.c | 52 void __iomem *reg_base; member 71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time() 92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time() 99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time() 135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable() 173 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); in xlnx_init_rtc() 175 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); in xlnx_init_rtc() 263 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_interrupt() 296 if (IS_ERR(xrtcdev->reg_base)) in xlnx_rtc_probe() 297 return PTR_ERR(xrtcdev->reg_base); in xlnx_rtc_probe() [all …]
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/linux/arch/arm/mach-rockchip/ |
H A D | rockchip.c | 25 void __iomem *reg_base; in rockchip_timer_init() local 32 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init() 33 if (reg_base) { in rockchip_timer_init() 34 writel(0, reg_base + 0x30); in rockchip_timer_init() 35 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init() 36 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init() 37 writel(1, reg_base + 0x30); in rockchip_timer_init() 39 iounmap(reg_base); in rockchip_timer_init()
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/linux/drivers/input/serio/ |
H A D | sun4i-ps2.c | 85 void __iomem *reg_base; member 118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt() 125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt() 154 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open() 161 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open() 175 writel(rval, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_open() 187 rval = readl(drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_close() 234 if (!drvdata->reg_base) { in sun4i_ps2_probe() 263 writel(0, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_probe() 293 iounmap(drvdata->reg_base); in sun4i_ps2_probe() [all …]
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/linux/arch/powerpc/boot/ |
H A D | ns16550.c | 31 static unsigned char *reg_base; variable 36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open() 42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc() 43 out_8(reg_base, c); in ns16550_putc() 48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc() 49 return in_8(reg_base); in ns16550_getc() 54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc() 62 if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) { in ns16550_console_init() 69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
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/linux/drivers/fpga/ |
H A D | altera-pr-ip-core.c | 29 void __iomem *reg_base; member 39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state() 90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init() 99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init() 116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write() 123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write() 126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write() 129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write() 176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument 186 priv->reg_base = reg_base; in alt_pr_register() [all …]
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