Searched refs:vdsc_cfg (Results 1 – 7 of 7) sorted by relevance
1321 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()1327 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()1336 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()1354 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()1370 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()1374 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()1380 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()1396 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()1426 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()1432 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()[all …]
107 if (vdsc_cfg->native_420) { in calculate_rc_params()115 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, in calculate_rc_params()138 if (vdsc_cfg->native_420) { in calculate_rc_params()246 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) in intel_dsc_slice_dimensions_valid()255 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) in intel_dsc_slice_dimensions_valid()272 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()304 if (vdsc_cfg->native_420) in intel_dsc_compute_params()343 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()344 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()456 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()[all …]
1571 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local1588 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()1590 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()1597 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()1598 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()1600 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()1601 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()1603 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()1605 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); in gen11_dsi_dsc_compute_config()
1710 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params() local1719 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dp_dsc_compute_params()1722 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); in intel_dp_dsc_compute_params()1728 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()1731 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()1734 if (vdsc_cfg->convert_rgb) in intel_dp_dsc_compute_params()1735 vdsc_cfg->convert_rgb = in intel_dp_dsc_compute_params()1739 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, in intel_dp_dsc_compute_params()1741 if (!vdsc_cfg->line_buf_depth) { in intel_dp_dsc_compute_params()1747 vdsc_cfg->block_pred_enable = in intel_dp_dsc_compute_params()[all …]
3499 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local3502 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()3503 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()3548 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, in fill_dsc()3552 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()3554 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()3556 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
1101 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check() local1133 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()2377 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment() local2383 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
24 void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);25 void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);26 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type);27 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);30 u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg);