| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 404 struct dc_writeback_info *wb_info, in dcn30_set_writeback() argument
411 ASSERT(wb_info->wb_enabled); in dcn30_set_writeback()
412 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
419 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
434 wb_info->mpcc_inst); in dcn30_update_writeback()
445 struct dc_writeback_info *wb_info) in dcn30_mmhubbub_warmup() argument
513 wb_info->mpcc_inst); in dcn30_enable_writeback()
553 struct dc_writeback_info wb_info; in dcn30_program_all_writeback_pipes_in_tree() local
574 if (wb_info.wb_enabled) { in dcn30_program_all_writeback_pipes_in_tree()
577 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
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| H A D | dcn30_hwseq.h | 40 struct dc_writeback_info *wb_info,
44 struct dc_writeback_info *wb_info,
53 struct dc_writeback_info *wb_info);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 280 if (wb_info->wb_enabled && wb_info->writeback_source_plane && in dcn30_fpu_populate_dml_writeback_from_context()
285 wb_info->dwb_params.cnv_params.crop_height : in dcn30_fpu_populate_dml_writeback_from_context()
286 wb_info->dwb_params.cnv_params.src_height; in dcn30_fpu_populate_dml_writeback_from_context()
288 wb_info->dwb_params.cnv_params.crop_width : in dcn30_fpu_populate_dml_writeback_from_context()
289 wb_info->dwb_params.cnv_params.src_width; in dcn30_fpu_populate_dml_writeback_from_context()
304 (double)wb_info->dwb_params.cnv_params.crop_width / in dcn30_fpu_populate_dml_writeback_from_context()
305 (double)wb_info->dwb_params.dest_width : in dcn30_fpu_populate_dml_writeback_from_context()
306 (double)wb_info->dwb_params.cnv_params.src_width / in dcn30_fpu_populate_dml_writeback_from_context()
307 (double)wb_info->dwb_params.dest_width; in dcn30_fpu_populate_dml_writeback_from_context()
310 (double)wb_info->dwb_params.dest_height : in dcn30_fpu_populate_dml_writeback_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 393 struct dc_writeback_info *wb_info) in dc_stream_add_writeback() argument
404 if (wb_info == NULL) { in dc_stream_add_writeback()
409 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
418 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
427 stream->writeback_info[i] = *wb_info; in dc_stream_add_writeback()
434 stream->writeback_info[stream->num_wb_info++] = *wb_info; in dc_stream_add_writeback()
439 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
455 dc->hwss.update_writeback(dc, wb_info, dc->current_state); in dc_stream_add_writeback()
458 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); in dc_stream_add_writeback()
552 struct dc_writeback_info *wb_info) in dc_stream_warmup_writeback() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_translation_helper.c | 1071 if (wb_info->wb_enabled) { in populate_dml_writeback_cfg_from_stream_state()
1078 wb_info->dwb_params.cnv_params.crop_width : in populate_dml_writeback_cfg_from_stream_state()
1079 wb_info->dwb_params.cnv_params.src_width; in populate_dml_writeback_cfg_from_stream_state()
1082 wb_info->dwb_params.cnv_params.crop_height : in populate_dml_writeback_cfg_from_stream_state()
1083 wb_info->dwb_params.cnv_params.src_height; in populate_dml_writeback_cfg_from_stream_state()
1086 wb_info->dwb_params.scaler_taps.h_taps : 1; in populate_dml_writeback_cfg_from_stream_state()
1088 wb_info->dwb_params.scaler_taps.v_taps : 1; in populate_dml_writeback_cfg_from_stream_state()
1092 (double)wb_info->dwb_params.dest_width : in populate_dml_writeback_cfg_from_stream_state()
1094 (double)wb_info->dwb_params.dest_width; in populate_dml_writeback_cfg_from_stream_state()
1097 (double)wb_info->dwb_params.dest_height : in populate_dml_writeback_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 2497 if (wb_info->wb_enabled && wb_info->writeback_source_plane && in dcn201_populate_dml_writeback_from_context_fpu()
2502 wb_info->dwb_params.cnv_params.crop_height : in dcn201_populate_dml_writeback_from_context_fpu()
2503 wb_info->dwb_params.cnv_params.src_height; in dcn201_populate_dml_writeback_from_context_fpu()
2505 wb_info->dwb_params.cnv_params.crop_width : in dcn201_populate_dml_writeback_from_context_fpu()
2506 wb_info->dwb_params.cnv_params.src_width; in dcn201_populate_dml_writeback_from_context_fpu()
2514 (double)wb_info->dwb_params.cnv_params.crop_width / in dcn201_populate_dml_writeback_from_context_fpu()
2515 (double)wb_info->dwb_params.dest_width : in dcn201_populate_dml_writeback_from_context_fpu()
2516 (double)wb_info->dwb_params.cnv_params.src_width / in dcn201_populate_dml_writeback_from_context_fpu()
2517 (double)wb_info->dwb_params.dest_width; in dcn201_populate_dml_writeback_from_context_fpu()
2520 (double)wb_info->dwb_params.dest_height : in dcn201_populate_dml_writeback_from_context_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 310 struct dc_writeback_info *wb_info,
313 struct dc_writeback_info *wb_info,
320 struct dc_writeback_info *wb_info);
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_stream.h | 404 struct dc_writeback_info *wb_info);
420 struct dc_writeback_info *wb_info);
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 9054 struct dc_writeback_info *wb_info; in dm_set_writeback() local
9059 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); in dm_set_writeback()
9060 if (!wb_info) { in dm_set_writeback()
9068 kfree(wb_info); in dm_set_writeback()
9075 kfree(wb_info); in dm_set_writeback()
9087 wb_info->wb_enabled = true; in dm_set_writeback()
9089 wb_info->dwb_pipe_inst = 0; in dm_set_writeback()
9091 wb_info->dwb_params.hdr_mult = 0x1F000; in dm_set_writeback()
9129 wb_info->mcif_buf_params.p_vmid = 1; in dm_set_writeback()
9133 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; in dm_set_writeback()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 116 struct dc_writeback_info *wb_info,
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| H A D | dcn20_hwseq.c | 2400 struct dc_writeback_info *wb_info, in dcn20_enable_writeback() argument
2407 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
2408 ASSERT(wb_info->wb_enabled); in dcn20_enable_writeback()
2409 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2410 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2414 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); in dcn20_enable_writeback()
2416 …mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_heigh… in dcn20_enable_writeback()
2417 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn20_enable_writeback()
2421 dwb->funcs->enable(dwb, &wb_info->dwb_params); in dcn20_enable_writeback()
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