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Searched refs:write_reg (Results 1 – 25 of 181) sorted by relevance

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/linux/drivers/staging/fbtft/
H A Dfb_bd663474.c36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
44 write_reg(par, 0x100, 0x3120); in init_display()
47 write_reg(par, 0x001, 0x0100); in init_display()
48 write_reg(par, 0x002, 0x0000); in init_display()
49 write_reg(par, 0x003, 0x1230); in init_display()
[all …]
H A Dfb_upd161704.c59 write_reg(par, 0x002E, 0x002D); in init_display()
119 write_reg(par, 0x0006, xs); in set_addr_win()
120 write_reg(par, 0x0007, ys); in set_addr_win()
128 write_reg(par, 0x0007, xs); in set_addr_win()
131 write_reg(par, 0x0006, ys); in set_addr_win()
144 write_reg(par, 0x01, 0x0000); in set_var()
145 write_reg(par, 0x05, 0x0000); in set_var()
148 write_reg(par, 0x01, 0x00C0); in set_var()
149 write_reg(par, 0x05, 0x0000); in set_var()
152 write_reg(par, 0x01, 0x0080); in set_var()
[all …]
H A Dfb_ili9320.c26 write_reg(par, 0x0000); in read_devicecode()
49 write_reg(par, 0x00E5, 0x8000); in init_display()
52 write_reg(par, 0x0000, 0x0001); in init_display()
55 write_reg(par, 0x0001, 0x0100); in init_display()
58 write_reg(par, 0x0002, 0x0700); in init_display()
61 write_reg(par, 0x0004, 0x0000); in init_display()
64 write_reg(par, 0x0008, 0x0202); in init_display()
169 write_reg(par, 0x0020, xs); in set_addr_win()
170 write_reg(par, 0x0021, ys); in set_addr_win()
178 write_reg(par, 0x0021, xs); in set_addr_win()
[all …]
H A Dfb_s6d1121.c33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
74 write_reg(par, 0x0020, xs); in set_addr_win()
75 write_reg(par, 0x0021, ys); in set_addr_win()
83 write_reg(par, 0x0021, xs); in set_addr_win()
[all …]
H A Dfb_ili9325.c138 write_reg(par, 0x0080, 0x0000); in init_display()
139 write_reg(par, 0x0081, 0x0000); in init_display()
140 write_reg(par, 0x0082, 0x0000); in init_display()
141 write_reg(par, 0x0083, 0x0000); in init_display()
142 write_reg(par, 0x0084, 0x0000); in init_display()
143 write_reg(par, 0x0085, 0x0000); in init_display()
146 write_reg(par, 0x0090, 0x0010); in init_display()
159 write_reg(par, 0x0020, xs); in set_addr_win()
160 write_reg(par, 0x0021, ys); in set_addr_win()
168 write_reg(par, 0x0021, xs); in set_addr_win()
[all …]
H A Dfb_ssd1289.c30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
36 write_reg(par, 0x01, in init_display()
61 write_reg(par, 0x22); in init_display()
71 write_reg(par, 0x4e, xs); in set_addr_win()
72 write_reg(par, 0x4f, ys); in set_addr_win()
80 write_reg(par, 0x4f, xs); in set_addr_win()
83 write_reg(par, 0x4e, ys); in set_addr_win()
[all …]
H A Dfb_ra8875.c55 write_reg(par, 0x88, 0x0A); in init_display()
56 write_reg(par, 0x89, 0x02); in init_display()
59 write_reg(par, 0x10, 0x0C); in init_display()
61 write_reg(par, 0x04, 0x03); in init_display()
64 write_reg(par, 0x14, 0x27); in init_display()
65 write_reg(par, 0x15, 0x00); in init_display()
66 write_reg(par, 0x16, 0x05); in init_display()
67 write_reg(par, 0x17, 0x04); in init_display()
68 write_reg(par, 0x18, 0x03); in init_display()
70 write_reg(par, 0x19, 0xEF); in init_display()
[all …]
H A Dfb_hx8347d.c28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
36 write_reg(par, 0x27, 0xA3); in init_display()
39 write_reg(par, 0x1B, 0x1B); in init_display()
[all …]
H A Dfb_tinylcd.c24 write_reg(par, 0xB0, 0x80); in init_display()
25 write_reg(par, 0xC0, 0x0A, 0x0A); in init_display()
26 write_reg(par, 0xC1, 0x45, 0x07); in init_display()
27 write_reg(par, 0xC2, 0x33); in init_display()
29 write_reg(par, 0xB1, 0xD0, 0x11); in init_display()
30 write_reg(par, 0xB4, 0x02); in init_display()
32 write_reg(par, 0xB7, 0x07); in init_display()
35 write_reg(par, 0xE5, 0x80); in init_display()
36 write_reg(par, 0xE5, 0x01); in init_display()
37 write_reg(par, 0xB3, 0x00); in init_display()
[all …]
H A Dfb_ssd1306.c46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
50 write_reg(par, 0x80); in init_display()
53 write_reg(par, 0xA8); in init_display()
55 write_reg(par, 0x3F); in init_display()
62 write_reg(par, 0xD3); in init_display()
63 write_reg(par, 0x0); in init_display()
69 write_reg(par, 0x8D); in init_display()
71 write_reg(par, 0x14); in init_display()
74 write_reg(par, 0x20); in init_display()
[all …]
H A Dfb_seps525.c103 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03); in init_display()
111 write_reg(par, SEPS525_OSC_CTL, 0x01); in init_display()
113 write_reg(par, SEPS525_CLOCK_DIV, 0x90); in init_display()
115 write_reg(par, SEPS525_IREF, 0x01); in init_display()
138 write_reg(par, SEPS525_DSL, 0x00); in init_display()
141 write_reg(par, SEPS525_SOFT_RST, 0x00); in init_display()
143 write_reg(par, SEPS525_RGB_POL, 0x00); in init_display()
154 write_reg(par, SEPS525_MX1_ADDR, xs); in set_addr_win()
155 write_reg(par, SEPS525_MX2_ADDR, xe); in set_addr_win()
156 write_reg(par, SEPS525_MY1_ADDR, ys); in set_addr_win()
[all …]
H A Dfb_ili9340.c25 write_reg(par, 0xEF, 0x03, 0x80, 0x02); in init_display()
30 write_reg(par, 0xF7, 0x20); in init_display()
31 write_reg(par, 0xEA, 0x00, 0x00); in init_display()
34 write_reg(par, 0xC0, 0x23); in init_display()
37 write_reg(par, 0xC1, 0x10); in init_display()
40 write_reg(par, 0xC5, 0x3e, 0x28); in init_display()
43 write_reg(par, 0xC7, 0x86); in init_display()
51 write_reg(par, 0xB1, 0x00, 0x18); in init_display()
57 write_reg(par, 0xF2, 0x00); in init_display()
63 write_reg(par, 0xE0, in init_display()
[all …]
H A Dfb_ssd1305.c47 write_reg(par, 0xAE); in init_display()
50 write_reg(par, 0xD5); in init_display()
51 write_reg(par, 0x80); in init_display()
54 write_reg(par, 0xA8); in init_display()
56 write_reg(par, 0x3F); in init_display()
61 write_reg(par, 0xD3); in init_display()
62 write_reg(par, 0x0); in init_display()
68 write_reg(par, 0x8D); in init_display()
70 write_reg(par, 0x14); in init_display()
73 write_reg(par, 0x20); in init_display()
[all …]
H A Dfb_ili9341.c34 write_reg(par, MIPI_DCS_SOFT_RESET); in init_display()
38 write_reg(par, 0xCF, 0x00, 0x83, 0x30); in init_display()
40 write_reg(par, 0xE8, 0x85, 0x01, 0x79); in init_display()
42 write_reg(par, 0xF7, 0x20); in init_display()
43 write_reg(par, 0xEA, 0x00, 0x00); in init_display()
45 write_reg(par, 0xC0, 0x26); in init_display()
46 write_reg(par, 0xC1, 0x11); in init_display()
48 write_reg(par, 0xC5, 0x35, 0x3E); in init_display()
49 write_reg(par, 0xC7, 0xBE); in init_display()
53 write_reg(par, 0xB1, 0x00, 0x1B); in init_display()
[all …]
H A Dfb_ssd1351.c40 write_reg(par, 0xae); /* Display Off */ in init_display()
47 write_reg(par, 0xb5, 0x00); /* Set GPIO */ in init_display()
64 write_reg(par, 0x15, xs, xe); in set_addr_win()
65 write_reg(par, 0x75, ys, ye); in set_addr_win()
66 write_reg(par, 0x5c); in set_addr_win()
91 write_reg(par, 0xA0, remap | 0x02); in set_var()
94 write_reg(par, 0xA0, remap | 0x01); in set_var()
144 write_reg(par, 0xB8, in set_gamma()
170 write_reg(par, 0xAE); in blank()
172 write_reg(par, 0xAF); in blank()
[all …]
H A Dfb_ssd1325.c38 write_reg(par, 0xb3); in init_display()
39 write_reg(par, 0xf0); in init_display()
40 write_reg(par, 0xae); in init_display()
41 write_reg(par, 0xa1); in init_display()
42 write_reg(par, 0x00); in init_display()
43 write_reg(par, 0xa8); in init_display()
44 write_reg(par, 0x3f); in init_display()
45 write_reg(par, 0xa0); in init_display()
46 write_reg(par, 0x45); in init_display()
47 write_reg(par, 0xa2); in init_display()
[all …]
H A Dfb_ili9163.c89 write_reg(par, MIPI_DCS_ENTER_NORMAL_MODE); in init_display()
90 write_reg(par, CMD_DFUNCTR, 0xff, 0x06); in init_display()
92 write_reg(par, CMD_FRMCTR1, 0x08, 0x02); in init_display()
95 write_reg(par, CMD_PWCTR1, 0x0A, 0x02); in init_display()
97 write_reg(par, CMD_PWCTR2, 0x02); in init_display()
99 write_reg(par, CMD_VCOMCTR1, 0x50, 0x63); in init_display()
100 write_reg(par, CMD_VCOMOFFS, 0); in init_display()
118 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, in set_addr_win()
126 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, in set_addr_win()
133 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, in set_addr_win()
[all …]
H A Dfb_hx8357d.c30 write_reg(par, MIPI_DCS_SOFT_RESET); in init_display()
41 write_reg(par, HX8357D_SETCOM, 0x25); in init_display()
44 write_reg(par, HX8357_SETOSC, 0x68); in init_display()
47 write_reg(par, HX8357_SETPANEL, 0x05); in init_display()
49 write_reg(par, HX8357_SETPWR1, in init_display()
57 write_reg(par, HX8357D_SETSTBA, in init_display()
65 write_reg(par, HX8357D_SETCYC, in init_display()
74 write_reg(par, HX8357D_SETGAMMA, in init_display()
122 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); in init_display()
126 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); in init_display()
[all …]
H A Dfb_uc1701.c68 write_reg(par, LCD_RESET_CMD); in init_display()
72 write_reg(par, LCD_START_LINE); in init_display()
81 write_reg(par, LCD_ALL_PIXEL | 0); in init_display()
87 write_reg(par, LCD_BIAS | 0); in init_display()
96 write_reg(par, LCD_VOLUME_MODE); in init_display()
97 write_reg(par, 0x09); in init_display()
98 write_reg(par, LCD_NO_OP); in init_display()
113 write_reg(par, LCD_PAGE_ADDRESS); in set_addr_win()
114 write_reg(par, 0x00); in set_addr_win()
115 write_reg(par, LCD_COL_ADDRESS); in set_addr_win()
[all …]
H A Dfb_ssd1331.c29 write_reg(par, 0xae); /* Display Off */ in init_display()
37 write_reg(par, 0x72); /* RGB colour */ in init_display()
40 write_reg(par, 0xa4); /* NORMALDISPLAY */ in init_display()
44 write_reg(par, 0xb1, 0x31); /* Precharge */ in init_display()
45 write_reg(par, 0xb3, 0xf0); /* Clock div */ in init_display()
50 write_reg(par, 0xbe, 0x3e); /* vcomh */ in init_display()
62 write_reg(par, 0x15, xs, xe); in set_addr_win()
63 write_reg(par, 0x75, ys, ye); in set_addr_win()
153 write_reg(par, 0xB8, in set_gamma()
173 write_reg(par, 0xAE); in blank()
[all …]
H A Dfb_hx8353d.c26 write_reg(par, 0xB9, 0xFF, 0x83, 0x53); in init_display()
29 write_reg(par, 0xB0, 0x3C, 0x01); in init_display()
32 write_reg(par, 0xB6, 0x94, 0x6C, 0x50); in init_display()
38 write_reg(par, 0x3A, 0x05); in init_display()
44 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); in init_display()
48 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); in init_display()
51 write_reg(par, MIPI_DCS_WRITE_LUT, in init_display()
73 write_reg(par, 0x2c); in set_addr_win()
91 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, in set_var()
95 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, in set_var()
[all …]
H A Dfb_hx8340bn.c45 write_reg(par, 0xC1, 0xFF, 0x83, 0x40); in init_display()
53 write_reg(par, 0x11); in init_display()
57 write_reg(par, 0xCA, 0x70, 0x00, 0xD9); in init_display()
65 write_reg(par, 0xB0, 0x01, 0x11); in init_display()
78 write_reg(par, 0xB5, 0x35, 0x20, 0x45); in init_display()
87 write_reg(par, 0xB4, 0x33, 0x25, 0x4C); in init_display()
103 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); in init_display()
128 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, in set_var()
132 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, in set_var()
172 write_reg(par, 0xC2, in set_gamma()
[all …]
H A Dfb_uc1611.c81 write_reg(par, 0xE2); in init_display()
87 write_reg(par, 0x81); in init_display()
117 write_reg(par, ys & 0x0F); in set_addr_win()
164 write_reg(par, 0x88 in set_var()
170 write_reg(par, 0xC0 in set_var()
177 write_reg(par, 0x88 in set_var()
183 write_reg(par, 0xC0 in set_var()
190 write_reg(par, 0x88 in set_var()
196 write_reg(par, 0xC0 in set_var()
203 write_reg(par, 0x88 in set_var()
[all …]
/linux/arch/sh/boards/mach-kfr2r09/
H A Dlcd_wqvga.c91 write_reg(sohandle, so, 0, 0xb0); in read_device_code()
92 write_reg(sohandle, so, 1, 0x00); in read_device_code()
95 write_reg(sohandle, so, 0, 0xb1); in read_device_code()
96 write_reg(sohandle, so, 1, 0x00); in read_device_code()
99 write_reg(sohandle, so, 0, 0xbf); in read_device_code()
117 write_reg(sohandle, so, 0, 0x2c); in write_memory_start()
137 write_reg(sohandle, so, 0, 0xb0); in display_on()
138 write_reg(sohandle, so, 1, 0x00); in display_on()
141 write_reg(sohandle, so, 0, 0xb1); in display_on()
142 write_reg(sohandle, so, 1, 0x00); in display_on()
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv0910.c202 return write_reg(state, field >> 16, new); in write_field()
572 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
846 write_reg(state, RSTV0910_NCOARSE2, odf); in set_mclock()
1089 write_reg(state, RSTV0910_TSTRES0, 0); in start()
1456 write_reg(state, in read_status()
1464 write_reg(state, in read_status()
1469 write_reg(state, in read_status()
1477 write_reg(state, in read_status()
1485 write_reg(state, in read_status()
1490 write_reg(state, in read_status()
[all …]

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