Searched refs:wrm_reg (Results 1 – 3 of 3) sorted by relevance
413 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()414 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()415 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()421 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()422 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()423 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()424 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
890 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()891 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()892 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()893 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()916 op_input.wrm_reg.reg0 = reg; in amdgpu_mes_reg_wait()917 op_input.wrm_reg.ref = val; in amdgpu_mes_reg_wait()918 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_wait()
309 } wrm_reg; member