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Searched refs:CTLZ (Results 1 – 25 of 27) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/PowerPC/
H A Dcttz-ctlz-spec.ll7 ; CHECK: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
8 ; CHECK-NEXT: ret i64 [[CTLZ]]
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/R600/
H A Dcttz-ctlz.ll7 ; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
8 ; SI-NEXT: ret i64 [[CTLZ]]
25 ; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i32 @llvm.ctlz.i32(i32 %A, i1 false)
26 ; SI-NEXT: ret i32 [[CTLZ]]
43 ; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i16 @llvm.ctlz.i16(i16 %A, i1 false)
44 ; SI-NEXT: ret i16 [[CTLZ]]
/minix/external/bsd/llvm/dist/llvm/test/Transforms/SLPVectorizer/X86/
H A Dnon-vectorizable-intrinsic.ll6 ; CTLZ cannot be vectorized currently because the second argument is a scalar
9 ; Test causes an assert if LLVM tries to vectorize CTLZ.
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/X86/
H A Dcttz-ctlz.ll8 ; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
9 ; LZCNT-NEXT: ret i64 [[CTLZ]]
30 ; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i32 @llvm.ctlz.i32(i32 %A, i1 false)
31 ; LZCNT-NEXT: ret i32 [[CTLZ]]
52 ; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i16 @llvm.ctlz.i16(i16 %A, i1 false)
53 ; LZCNT-NEXT: ret i16 [[CTLZ]]
/minix/external/bsd/llvm/dist/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
255 Value *Tmp0 = Builder.CreateCall2(CTLZ, Divisor, True); in generateUnsignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall2(CTLZ, Dividend, True); in generateUnsignedDivisionCode()
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h319 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp293 case ISD::CTLZ: return "ctlz"; in getOperationName()
H A DLegalizeDAG.cpp2771 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); in ExpandBitCount()
2772 case ISD::CTLZ: { in ExpandBitCount()
2808 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount()
2811 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); in ExpandBitCount()
2957 case ISD::CTLZ: in ExpandNode()
4134 case ISD::CTLZ: in PromoteNode()
4149 } else if (Node->getOpcode() == ISD::CTLZ || in PromoteNode()
H A DLegalizeVectorTypes.cpp71 case ISD::CTLZ: in ScalarizeVectorResult()
612 case ISD::CTLZ: in SplitVectorResult()
1308 case ISD::CTLZ: in SplitVectorOperand()
1776 case ISD::CTLZ: in WidenVectorResult()
H A DLegalizeVectorOps.cpp277 case ISD::CTLZ: in LegalizeOp()
H A DLegalizeIntegerTypes.cpp62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
1236 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
H A DDAGCombiner.cpp1299 case ISD::CTLZ: return visitCTLZ(N); in visit()
4473 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
4569 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); in visitCTLZ()
12228 TLI.isOperationLegal(ISD::CTLZ, XType))) { in SimplifySelectCC()
12229 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0); in SimplifySelectCC()
H A DTargetLowering.cpp1241 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
H A DSelectionDAG.cpp2141 case ISD::CTLZ: in computeKnownBits()
2699 case ISD::CTLZ: in getNode()
/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp125 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
126 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1409 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in HexagonTargetLowering()
1410 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in HexagonTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp246 setOperationAction(ISD::CTLZ, MVT::i16, Legal); in NVPTXTargetLowering()
247 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in NVPTXTargetLowering()
248 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in NVPTXTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp270 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
341 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp262 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType()
2029 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
H A DMipsISelLowering.cpp367 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in MipsTargetLowering()
369 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in MipsTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1476 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1531 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp209 setOperationAction(ISD::CTLZ, MVT::i32, Promote); in SystemZTargetLowering()
210 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
/minix/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td364 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp494 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); in resetOperationActions()
495 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); in resetOperationActions()
503 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); in resetOperationActions()
504 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); in resetOperationActions()
505 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); in resetOperationActions()
510 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); in resetOperationActions()
859 setOperationAction(ISD::CTLZ, VT, Expand); in resetOperationActions()
1517 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal); in resetOperationActions()
1518 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal); in resetOperationActions()
19679 case ISD::CTLZ: return LowerCTLZ(Op, DAG); in LowerOperation()
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp459 setOperationAction(ISD::CTLZ, VT, Expand); in PPCTargetLowering()
1866 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC()

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