/minix/external/bsd/llvm/dist/llvm/test/CodeGen/PowerPC/ |
H A D | cttz-ctlz-spec.ll | 7 ; CHECK: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false) 8 ; CHECK-NEXT: ret i64 [[CTLZ]]
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/R600/ |
H A D | cttz-ctlz.ll | 7 ; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false) 8 ; SI-NEXT: ret i64 [[CTLZ]] 25 ; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i32 @llvm.ctlz.i32(i32 %A, i1 false) 26 ; SI-NEXT: ret i32 [[CTLZ]] 43 ; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i16 @llvm.ctlz.i16(i16 %A, i1 false) 44 ; SI-NEXT: ret i16 [[CTLZ]]
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/minix/external/bsd/llvm/dist/llvm/test/Transforms/SLPVectorizer/X86/ |
H A D | non-vectorizable-intrinsic.ll | 6 ; CTLZ cannot be vectorized currently because the second argument is a scalar 9 ; Test causes an assert if LLVM tries to vectorize CTLZ.
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/X86/ |
H A D | cttz-ctlz.ll | 8 ; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false) 9 ; LZCNT-NEXT: ret i64 [[CTLZ]] 30 ; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i32 @llvm.ctlz.i32(i32 %A, i1 false) 31 ; LZCNT-NEXT: ret i32 [[CTLZ]] 52 ; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i16 @llvm.ctlz.i16(i16 %A, i1 false) 53 ; LZCNT-NEXT: ret i16 [[CTLZ]]
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/minix/external/bsd/llvm/dist/llvm/lib/Transforms/Utils/ |
H A D | IntegerDivision.cpp | 183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local 255 Value *Tmp0 = Builder.CreateCall2(CTLZ, Divisor, True); in generateUnsignedDivisionCode() 256 Value *Tmp1 = Builder.CreateCall2(CTLZ, Dividend, True); in generateUnsignedDivisionCode()
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/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 319 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
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/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 293 case ISD::CTLZ: return "ctlz"; in getOperationName()
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H A D | LegalizeDAG.cpp | 2771 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); in ExpandBitCount() 2772 case ISD::CTLZ: { in ExpandBitCount() 2808 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount() 2811 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); in ExpandBitCount() 2957 case ISD::CTLZ: in ExpandNode() 4134 case ISD::CTLZ: in PromoteNode() 4149 } else if (Node->getOpcode() == ISD::CTLZ || in PromoteNode()
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H A D | LegalizeVectorTypes.cpp | 71 case ISD::CTLZ: in ScalarizeVectorResult() 612 case ISD::CTLZ: in SplitVectorResult() 1308 case ISD::CTLZ: in SplitVectorOperand() 1776 case ISD::CTLZ: in WidenVectorResult()
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H A D | LegalizeVectorOps.cpp | 277 case ISD::CTLZ: in LegalizeOp()
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H A D | LegalizeIntegerTypes.cpp | 62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult() 1236 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
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H A D | DAGCombiner.cpp | 1299 case ISD::CTLZ: return visitCTLZ(N); in visit() 4473 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL() 4569 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); in visitCTLZ() 12228 TLI.isOperationLegal(ISD::CTLZ, XType))) { in SimplifySelectCC() 12229 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0); in SimplifySelectCC()
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H A D | TargetLowering.cpp | 1241 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
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H A D | SelectionDAG.cpp | 2141 case ISD::CTLZ: in computeKnownBits() 2699 case ISD::CTLZ: in getNode()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 125 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering() 126 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1409 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in HexagonTargetLowering() 1410 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in HexagonTargetLowering()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 246 setOperationAction(ISD::CTLZ, MVT::i16, Legal); in NVPTXTargetLowering() 247 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in NVPTXTargetLowering() 248 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in NVPTXTargetLowering()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 270 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering() 341 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 262 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType() 2029 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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H A D | MipsISelLowering.cpp | 367 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in MipsTargetLowering() 369 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in MipsTargetLowering()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1476 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering() 1531 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 209 setOperationAction(ISD::CTLZ, MVT::i32, Promote); in SystemZTargetLowering() 210 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
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/minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 364 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
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/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 494 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); in resetOperationActions() 495 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); in resetOperationActions() 503 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); in resetOperationActions() 504 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); in resetOperationActions() 505 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); in resetOperationActions() 510 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); in resetOperationActions() 859 setOperationAction(ISD::CTLZ, VT, Expand); in resetOperationActions() 1517 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal); in resetOperationActions() 1518 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal); in resetOperationActions() 19679 case ISD::CTLZ: return LowerCTLZ(Op, DAG); in LowerOperation()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 459 setOperationAction(ISD::CTLZ, VT, Expand); in PPCTargetLowering() 1866 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC()
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