| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 45 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
107 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
155 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg); in MoveCopyOutOfITBlock()
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
195 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
212 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg); in InsertITInstructions()
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| H A D | Thumb2RegisterInfo.h | 33 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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| H A D | ARMBaseInstrInfo.h | 129 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
131 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() in getPredicate()
440 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
461 ARMCC::CondCodes Pred, unsigned PredReg,
467 ARMCC::CondCodes Pred, unsigned PredReg,
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| H A D | ARMLoadStoreOptimizer.cpp | 103 ARMCC::CondCodes Pred, unsigned PredReg);
119 ARMCC::CondCodes Pred,
126 ARMCC::CondCodes Pred, unsigned PredReg,
475 int Opcode, ARMCC::CondCodes Pred, in MergeOps()
820 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR()
1097 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSMultiple()
1254 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLoadStore()
1490 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in FixInvalidRegPairOp()
1585 ARMCC::CondCodes CurrPred = ARMCC::AL; in LoadStoreMultipleOpti()
1609 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg); in LoadStoreMultipleOpti()
[all …]
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| H A D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
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| H A D | Thumb1RegisterInfo.h | 41 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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| H A D | Thumb2InstrInfo.h | 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| H A D | MLxExpansionPass.cpp | 284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
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| H A D | ARMBaseRegisterInfo.h | 172 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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| H A D | ARMBaseInstrInfo.cpp | 166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); in convertToThreeAddress()
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in ReverseBranchCondition()
485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
1731 ARMCC::CondCodes
1740 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); in getInstrPredicate()
1763 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
2307 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { in getSwappedCondition()
2488 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> in optimizeCompareInstr()
2509 ARMCC::CondCodes CC; in optimizeCompareInstr()
[all …]
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| H A D | Thumb2SizeReduction.cpp | 153 bool is2Addr, ARMCC::CondCodes Pred,
292 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
685 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
782 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| H A D | ARMBaseRegisterInfo.cpp | 408 ARMCC::CondCodes Pred, in emitLoadConstPool()
759 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
760 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
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| H A D | Thumb2InstrInfo.cpp | 62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
224 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
633 ARMCC::CondCodes
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| H A D | ARMConstantIslandPass.cpp | 1361 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1597 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm(); in fixupConditionalBr()
1812 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
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| H A D | ARMFrameLowering.cpp | 119 ARMCC::CondCodes Pred = ARMCC::AL, in emitRegPlusImmediate()
133 ARMCC::CondCodes Pred = ARMCC::AL, in emitSPUpdate()
1794 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateCallFramePseudoInstr()
1795 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); in eliminateCallFramePseudoInstr()
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| H A D | Thumb1RegisterInfo.cpp | 67 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
228 MSP430CC::CondCodes BranchCode = in AnalyzeBranch()
229 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in AnalyzeBranch()
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
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| H A D | MSP430.h | 23 enum CondCodes { enum
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMBaseInfo.h | 29 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
47 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 34 enum CondCodes { enum
44 inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) { in NVPTXCondCodeToString()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | Sparc.h | 42 enum CondCodes { enum
79 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
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| H A D | SparcInstrInfo.cpp | 88 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
182 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); in AnalyzeBranch()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/InstPrinter/ |
| H A D | SparcInstPrinter.cpp | 170 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 916 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
927 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2480 unsigned *CondCodes = nullptr; in selectCmp() local
2485 CondCodes = &CondCodeTable[0][0]; in selectCmp()
2488 CondCodes = &CondCodeTable[1][0]; in selectCmp()
2492 if (CondCodes) { in selectCmp()
2498 .addImm(CondCodes[0]); in selectCmp()
2503 .addImm(CondCodes[1]); in selectCmp()
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