/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | AMDGPUSubtarget.cpp | 49 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef GPU, StringRef FS) { in initializeSubtargetDependencies() argument 62 ParseSubtargetFeatures(GPU, FullFS); in initializeSubtargetDependencies() 74 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, in AMDGPUSubtarget() argument 76 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), in AMDGPUSubtarget() 84 DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))), in AMDGPUSubtarget() 88 InstrItins(getInstrItineraryForCPU(GPU)), in AMDGPUSubtarget()
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H A D | AMDGPU.td | 82 "GPU has CF_ALU bug">; 133 Value#" GPU generation", Implies>;
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H A D | AMDGPUSubtarget.h | 84 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef GPU, StringRef FS);
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H A D | CaymanInstructions.td | 137 // This is not really necessary, but there were some GPU hangs that appeared
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H A D | EvergreenInstructions.td | 161 // This is not really necessary, but there were some GPU hangs that appeared
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H A D | SIInstructions.td | 9 // This file was originally auto-generated from a GPU register header file and 69 // and writing to M0 from an SMRD instruction will hang the GPU.
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/minix/external/bsd/llvm/dist/llvm/docs/ |
H A D | NVPTXUsage.rst | 13 To support GPU programming, the NVPTX back-end supports a subset of LLVM IR 14 along with a defined set of conventions used to represent GPU programming 375 The most common way to execute PTX assembly on a GPU device is to use the CUDA 376 Driver API. This API is a low-level interface to the GPU driver and allows for 377 JIT compilation of PTX code to native GPU machine code. 577 an explicit address space specifier. What is address space 1? NVIDIA GPU 600 program), or a `device` function (callable only from GPU code). You can think 601 of `kernel` functions as entry-points in the GPU program. To mark an LLVM IR 630 a real GPU device? The CUDA Driver API provides a convenient mechanism for 631 loading and JIT compiling PTX to a native GPU device, and launching a kernel. [all …]
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H A D | CompilerWriterInfo.rst | 78 * `AMD GPU Programming Guide <http://developer.amd.com/download/AMD_Accelerated_Parallel_Processing…
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H A D | index.rst | 318 This document describes using the NVPTX back-end to compile GPU kernels.
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/minix/external/bsd/llvm/dist/clang/lib/Basic/ |
H A D | Targets.cpp | 1408 } GPU; member in __anonb5624ff00811::NVPTXTargetInfo 1421 GPU = GK_SM20; in NVPTXTargetInfo() 1430 switch (GPU) { in getTargetDefines() 1490 GPU = llvm::StringSwitch<GPUKind>(Name) in setCPU() 1497 return GPU != GK_NONE; in setCPU() 1583 } GPU; member in __anonb5624ff00911::R600TargetInfo 1587 : TargetInfo(Triple), GPU(GK_R600) { in R600TargetInfo() 1594 if (GPU <= GK_CAYMAN) in getPointerWidthV() 1644 GPU = llvm::StringSwitch<GPUKind>(Name) in setCPU() 1682 if (GPU == GK_NONE) { in setCPU() [all …]
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/minix/external/bsd/llvm/dist/llvm/docs/TableGen/ |
H A D | BackEnds.rst | 184 **Output**: Scheduling tables for GPU back-ends (Hexagon, AMD).
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/minix/external/bsd/llvm/dist/clang/include/clang/Basic/ |
H A D | AttrDocs.td | 677 DocumentationCategory<"AMD GPU Register Attributes"> { 679 Clang supports attributes for controlling register usage on AMD GPU
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H A D | Attr.td | 878 // However, only AMD GPU targets will emit the corresponding IR
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/minix/share/misc/ |
H A D | acronyms.comp | 491 GPU graphics processing unit
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/R600/ |
H A D | si-sgpr-spill.ll | 9 ; Writing to M0 from an SMRD instruction will hang the GPU.
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/minix/sys/dev/pci/ |
H A D | pcidevs | 1518 product ATI RADEON_HD4250_S 0x95c5 Radeon HD4250 GPU (RV610) Secondary 1521 product ATI RADEON_HD4250 0x9715 Radeon HD4250 GPU (RS880) 4741 product NVIDIA GEFORCE2_IGP 0x01a0 GeForce2 Integrated GPU 4764 product NVIDIA GF4_MX_IGP 0x01f0 GeForce4 MX Integrated GPU
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/minix/games/fortune/datfiles/ |
H A D | fortunes2 | 9832 of freight trains and not worry about heavier than average loads. The GPU
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