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Searched refs:SETNE (Results 1 – 25 of 33) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSelectCCInfo.td20 IntRegs:$fval, SETNE)),
80 // and similarly for SETNE
83 IntRegs:$fval, SETNE)),
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp133 case ISD::SETNE: in softenSetCCOperands()
1245 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1250 Cond = ISD::SETNE; in SimplifySetCC()
1288 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1413 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
1430 case ISD::SETNE: in SimplifySetCC()
1619 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
1622 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
1655 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1827 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
[all …]
H A DLegalizeIntegerTypes.cpp513 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
688 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
888 case ISD::SETNE: { in PromoteSetCCOperands()
1880 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1910 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2136 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2400 ISD::SETNE); in ExpandIntRes_XMULO()
2461 ISD::SETNE); in ExpandIntRes_XMULO()
2624 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { in IntegerExpandSetCCOperands()
2730 CCCode = ISD::SETNE; in ExpandIntOp_BR_CC()
[all …]
H A DLegalizeDAG.cpp1723 case ISD::SETNE: in LegalizeSetCCCondCode()
1726 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ; in LegalizeSetCCCondCode()
2522 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); in ExpandLegalINT_TO_FP()
3739 ISD::SETEQ : ISD::SETNE); in ExpandNode()
3742 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandNode()
3840 ISD::SETNE); in ExpandNode()
3843 DAG.getConstant(0, VT), ISD::SETNE); in ExpandNode()
3870 Tmp2, Tmp3, ISD::SETNE); in ExpandNode()
3922 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
4034 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
[all …]
H A DLegalizeFloatTypes.cpp759 CCCode = ISD::SETNE; in SoftenFloatOp_BR_CC()
798 CCCode = ISD::SETNE; in SoftenFloatOp_SELECT_CC()
1440 CCCode = ISD::SETNE; in ExpandFloatOp_BR_CC()
1533 CCCode = ISD::SETNE; in ExpandFloatOp_SELECT_CC()
H A DSelectionDAGDumper.cpp324 case ISD::SETNE: return "setne"; in getOperationName()
H A DSelectionDAGBuilder.cpp1563 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) in ShouldEmitAsBranches()
1853 Sub, DAG.getConstant(0, VT), ISD::SETNE); in visitSPDescriptorParent()
1971 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE); in visitBitTestCase()
1982 DAG.getConstant(0, VT), ISD::SETNE); in visitBitTestCase()
5906 ISD::SETNE); in visitMemCmpCall()
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h797 SETNE, // 1 X 1 1 0 True if not equal enumerator
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h428 X86_INTRINSIC_DATA(sse2_comineq_sd, COMI, X86ISD::COMI, ISD::SETNE),
468 X86_INTRINSIC_DATA(sse2_ucomineq_sd, COMI, X86ISD::UCOMI, ISD::SETNE),
501 X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
510 X86_INTRINSIC_DATA(sse_ucomineq_ss, COMI, X86ISD::UCOMI, ISD::SETNE),
H A DX86InstrCMovSetCC.td101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp674 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
675 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
676 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
689 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
690 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
691 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
H A DAnalysis.cpp186 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
201 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DAMDGPUInstructions.td78 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
120 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
143 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
H A DR600ISelLowering.cpp1086 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1217 case ISD::SETNE: in LowerSELECT_CC()
1255 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1983 case ISD::SETNE: return LHS; in PerformDAGCombine()
H A DR600Instructions.td700 0xB, "SETNE",
795 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp193 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); in ARMTargetLowering()
194 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); in ARMTargetLowering()
195 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); in ARMTargetLowering()
196 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); in ARMTargetLowering()
1217 case ISD::SETNE: return ARMCC::NE; in IntCCToARMCC()
1254 case ISD::SETNE: in FPCCToARMCC()
3496 if (CC == ISD::SETNE) in getInverseCCForVSEL()
3593 CC = ISD::SETNE; in LowerSELECT_CC()
3765 CC = ISD::SETNE; in OptimizeVFPBrcond()
3812 CC = ISD::SETNE; in LowerBR_CC()
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td2662 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2733 defm : ExtSetCCPat<SETNE,
2842 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2844 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2847 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2870 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2910 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2912 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2938 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2967 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
[all …]
H A DPPCISelDAGToDAG.cpp1951 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
1992 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2053 case ISD::SETNE: return PPC::PRED_NE; in getPredicateForSetCC()
2089 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
2123 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2167 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2228 case ISD::SETNE: { in SelectSETCC()
2261 case ISD::SETNE: { in SelectSETCC()
2656 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && in Select()
H A DPPCInstrVSX.td916 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
929 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
H A DPPCISelLowering.cpp1839 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in LowerSETCC()
1884 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1916 DAG.getConstant(0, MVT::i32), ISD::SETNE); in LowerVAARG()
5373 case ISD::SETNE: in LowerSELECT_CC()
5405 case ISD::SETNE: in LowerSELECT_CC()
9146 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
9151 (CC == ISD::SETNE && !Val); in PerformDAGCombine()
9167 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1363 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1369 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1376 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1382 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1328 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1347 case ISD::SETNE: in FPCondCCodeToFCC()
1744 CC == ISD::SETNE && in LookThroughSetCC()
2756 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
2759 ISD::SETNE); in LowerUMULO_SMULO()
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp969 case ISD::SETNE: in changeIntCCToAArch64CC()
1046 case ISD::SETNE: in changeFPCCToAArch64CC()
1106 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitComparison()
1208 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) { in getAArch64Cmp()
3215 CC = ISD::SETNE; in LowerBR_CC()
3226 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && in LowerBR_CC()
3237 if (CC == ISD::SETNE) in LowerBR_CC()
3268 } else if (CC == ISD::SETNE) { in LowerBR_CC()
3578 FVal, ISD::SETNE); in LowerSELECT()
3599 CC = ISD::SETNE; in LowerSELECT_CC()
/minix/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td531 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
899 (setcc node:$lhs, node:$rhs, SETNE)>;
/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp830 case ISD::SETNE: in EmitCMP()

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