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Searched refs:SREM (Results 1 – 25 of 28) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp525 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
529 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
533 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
537 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
542 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
546 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
550 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
554 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h186 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1087 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1092 setOperationAction(ISD::SREM, MVT::i64, Expand); in HexagonTargetLowering()
1289 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1324 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1327 setOperationAction(ISD::SREM, MVT::i64, Expand); in HexagonTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp171 case ISD::SREM: return "srem"; in getOperationName()
H A DSelectionDAGBuilder.h731 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
H A DLegalizeVectorOps.cpp261 case ISD::SREM: in LegalizeOp()
H A DLegalizeVectorTypes.cpp118 case ISD::SREM: in ScalarizeVectorResult()
669 case ISD::SREM: in SplitVectorResult()
1747 case ISD::SREM: in WidenVectorResult()
H A DSelectionDAG.cpp2277 case ISD::SREM: in computeKnownBits()
3037 case ISD::SREM: in FoldConstantArithmetic()
3144 case ISD::SREM: in getNode()
3473 case ISD::SREM: in getNode()
3501 case ISD::SREM: in getNode()
H A DLegalizeDAG.cpp2200 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; in useDivRem()
3588 case ISD::SREM: { in ExpandNode()
3590 bool isSigned = Node->getOpcode() == ISD::SREM; in ExpandNode()
H A DFastISel.cpp1484 return selectBinaryOp(I, ISD::SREM); in selectOperator()
H A DLegalizeIntegerTypes.cpp113 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; in PromoteIntegerResult()
1247 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; in ExpandIntegerResult()
H A DDAGCombiner.cpp1281 case ISD::SREM: return visitSREM(N); in visit()
2202 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); in visitSREM()
2494 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); in visitSDIVREM()
/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp158 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
164 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp891 case ISD::SREM: in canOpTrap()
1400 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp170 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
217 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
267 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2002 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
H A DMipsISelLowering.cpp280 setOperationAction(ISD::SREM, MVT::i32, Expand); in MipsTargetLowering()
284 setOperationAction(ISD::SREM, MVT::i64, Expand); in MipsTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp173 setOperationAction(ISD::SREM, MVT::i64, Custom); in R600TargetLowering()
901 case ISD::SREM: { in ReplaceNodeResults()
H A DAMDGPUISelLowering.cpp257 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
323 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4449 case ISD::SREM: in selectRem()
4896 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
4897 return selectRem(I, ISD::SREM); in fastSelectInstruction()
H A DAArch64ISelLowering.cpp255 setOperationAction(ISD::SREM, MVT::i32, Expand); in AArch64TargetLowering()
256 setOperationAction(ISD::SREM, MVT::i64, Expand); in AArch64TargetLowering()
644 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); in addTypeForNEON()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1408 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1415 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
/minix/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td338 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp142 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
144 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
425 setOperationAction(ISD::SREM, VT, Expand); in PPCTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp152 setOperationAction(ISD::SREM, VT, Expand); in SystemZTargetLowering()
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp436 setOperationAction(ISD::SREM, VT, Expand); in resetOperationActions()
826 setOperationAction(ISD::SREM, VT, Expand); in resetOperationActions()
1661 setOperationAction(ISD::SREM, MVT::i128, Custom); in resetOperationActions()
18297 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break; in LowerWin64_i128OP()
19741 case ISD::SREM: in ReplaceNodeResults()

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