| /minix/external/bsd/llvm/dist/llvm/test/CodeGen/X86/ |
| H A D | vshift-6.ll | 13 ; VSELECT(r, B, count);
17 ; r = VSELECT(r, C, count);
19 ; VSELECT(r, r+r, count);
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| H A D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 335 VSELECT, enumerator
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| H A D | SelectionDAG.h | 737 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
98 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
275 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
320 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
1089 case ISD::VSELECT: in PerformDAGCombine()
1580 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1593 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1601 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1608 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1639 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
442 case ISD::VSELECT: in ScalarizeVectorOperand()
583 case ISD::VSELECT: in SplitVectorResult()
1304 case ISD::VSELECT: in SplitVectorOperand()
1366 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
1368 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
1713 case ISD::VSELECT: in WidenVectorResult()
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| H A D | LegalizeVectorOps.cpp | 283 case ISD::VSELECT: in LegalizeOp()
681 case ISD::VSELECT: in Expand()
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| H A D | SelectionDAGDumper.cpp | 198 case ISD::VSELECT: return "vselect"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
544 return DAG.getNode(ISD::VSELECT, SDLoc(N), in PromoteIntRes_VSELECT()
839 case ISD::VSELECT: in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 1305 case ISD::VSELECT: return visitVSELECT(N); in visit()
7554 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, in visitFSQRT()
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| H A D | SelectionDAG.cpp | 6503 case ISD::VSELECT: in UnrollVectorOp()
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| H A D | SelectionDAGBuilder.cpp | 2956 ISD::VSELECT : ISD::SELECT; in visitSelect()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | BasicTargetTransformInfo.cpp | 466 ISD = ISD::VSELECT; in getCmpSelInstrCost()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 882 setOperationAction(ISD::VSELECT, VT, Expand); in resetOperationActions()
1670 setTargetDAGCombine(ISD::VSELECT); in resetOperationActions()
7529 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8, in lowerVectorShuffleAsBlend()
18886 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); in LowerShift()
18897 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); in LowerShift()
18905 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, in LowerShift()
19630 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
23486 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) { in PerformSELECTCombine()
23574 if (I->getOpcode() != ISD::VSELECT) in PerformSELECTCombine()
23612 if ((N->getOpcode() == ISD::VSELECT || in PerformSELECTCombine()
[all …]
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| H A D | X86ISelDAGToDAG.cpp | 2137 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0), in Select()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelLowering.cpp | 334 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
373 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 463 setOperationAction(ISD::VSELECT, VT, Expand); in PPCTargetLowering()
543 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in PPCTargetLowering()
544 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); in PPCTargetLowering()
545 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in PPCTargetLowering()
546 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
547 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in PPCTargetLowering()
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| H A D | PPCISelDAGToDAG.cpp | 2722 case ISD::VSELECT: in Select()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 414 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 471 setTargetDAGCombine(ISD::VSELECT); in AArch64TargetLowering()
633 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand); in addTypeForNEON()
8450 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
8530 case ISD::VSELECT: in PerformDAGCombine()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 122 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
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