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Searched refs:VecVT (Results 1 – 11 of 11) sorted by relevance

/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp372 EVT VecVT = N->getValueType(0); in ExpandOp_BUILD_VECTOR() local
373 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_BUILD_VECTOR()
378 assert(OldVT == VecVT.getVectorElementType() && in ExpandOp_BUILD_VECTOR()
401 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
412 EVT VecVT = N->getValueType(0); in ExpandOp_INSERT_VECTOR_ELT() local
413 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_INSERT_VECTOR_ELT()
420 assert(OldEVT == VecVT.getVectorElementType() && in ExpandOp_INSERT_VECTOR_ELT()
443 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp826 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
827 EVT SubVecVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_SUBVECTOR()
828 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in SplitVecRes_INSERT_SUBVECTOR()
834 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); in SplitVecRes_INSERT_SUBVECTOR()
904 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_VECTOR_ELT() local
905 EVT EltVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_VECTOR_ELT()
906 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in SplitVecRes_INSERT_VECTOR_ELT()
913 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); in SplitVecRes_INSERT_VECTOR_ELT()
1430 EVT VecVT = Vec.getValueType(); in SplitVecOp_EXTRACT_VECTOR_ELT() local
1453 EVT EltVT = VecVT.getVectorElementType(); in SplitVecOp_EXTRACT_VECTOR_ELT()
[all …]
H A DLegalizeIntegerTypes.cpp988 EVT VecVT = N->getValueType(0); in PromoteIntOp_BUILD_VECTOR() local
989 unsigned NumElts = VecVT.getVectorNumElements(); in PromoteIntOp_BUILD_VECTOR()
990 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && in PromoteIntOp_BUILD_VECTOR()
H A DDAGCombiner.cpp10827 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); in reduceBuildVecExtToExtBuildVec() local
10828 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && in reduceBuildVecExtToExtBuildVec()
10831 if (!isTypeLegal(VecVT)) return SDValue(); in reduceBuildVecExtToExtBuildVec()
10834 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); in reduceBuildVecExtToExtBuildVec()
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2110 if (VecVT.isFloatingPoint()) { in getVCmpInst()
2133 if (VecVT == MVT::v4f32) in getVCmpInst()
2135 else if (VecVT == MVT::v2f64) in getVCmpInst()
2140 if (VecVT == MVT::v4f32) in getVCmpInst()
2142 else if (VecVT == MVT::v2f64) in getVCmpInst()
2147 if (VecVT == MVT::v4f32) in getVCmpInst()
2149 else if (VecVT == MVT::v2f64) in getVCmpInst()
2177 if (VecVT == MVT::v16i8) in getVCmpInst()
2185 if (VecVT == MVT::v16i8) in getVCmpInst()
2193 if (VecVT == MVT::v16i8) in getVCmpInst()
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1534 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize); in LowerCall() local
1574 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext())); in LowerCall()
2189 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2); in LowerFormalArguments() local
2193 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, in LowerFormalArguments()
2195 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext()))); in LowerFormalArguments()
2227 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize); in LowerFormalArguments() local
2231 PointerType::get(VecVT.getTypeForEVT(F->getContext()), in LowerFormalArguments()
2237 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false, in LowerFormalArguments()
2239 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext()))); in LowerFormalArguments()
2396 EVT VecVT = in LowerReturn() local
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/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3346 EVT VecVT; in LowerFCOPYSIGN() local
3351 VecVT = MVT::v4i32; in LowerFCOPYSIGN()
3355 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, in LowerFCOPYSIGN()
3357 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, in LowerFCOPYSIGN()
3360 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); in LowerFCOPYSIGN()
3361 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); in LowerFCOPYSIGN()
3365 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
3373 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT, in LowerFCOPYSIGN()
3378 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); in LowerFCOPYSIGN()
3379 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); in LowerFCOPYSIGN()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2659 MVT VecVT = MVT::Other; in LowerFormalArguments() local
2664 VecVT = MVT::v16f32; in LowerFormalArguments()
2666 VecVT = MVT::v8f32; in LowerFormalArguments()
2668 VecVT = MVT::v4f32; in LowerFormalArguments()
2674 if (VecVT != MVT::Other) in LowerFormalArguments()
2675 RegParmTypes.push_back(VecVT); in LowerFormalArguments()
4980 MVT VecVT = N->getSimpleValueType(0); in getInsertVINSERTImmediate() local
6943 EVT VecVT = MVT::v4i32; in LowerBUILD_VECTOR() local
6966 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), in LowerBUILD_VECTOR()
12860 if (VecVT.is512BitVector() || in LowerEXTRACT_VECTOR_ELT()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2778 EVT VecVT = N->getValueType(0); in Select() local
2779 EVT EltVT = VecVT.getVectorElementType(); in Select()
2780 unsigned NumElts = VecVT.getVectorNumElements(); in Select()
2783 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)); in Select()
2787 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)); in Select()
2789 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1), in Select()
H A DARMISelLowering.cpp5257 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in LowerBUILD_VECTOR() local
5258 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
5290 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerBUILD_VECTOR() local
5294 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
5744 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerVECTOR_SHUFFLE() local
5745 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
5746 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
5757 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerVECTOR_SHUFFLE()
8773 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in PerformARMBUILD_VECTORCombine() local
8776 if (!TLI.isTypeLegal(VecVT)) in PerformARMBUILD_VECTORCombine()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp929 EVT VecVT = Vector.getValueType(); in vectorToVerticalVector() local
930 EVT EltVT = VecVT.getVectorElementType(); in vectorToVerticalVector()
933 for (unsigned i = 0, e = VecVT.getVectorNumElements(); in vectorToVerticalVector()
939 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()