/minix/external/bsd/llvm/dist/clang/test/CodeGen/ |
H A D | tbaa.cpp | 11 uint16_t f16; member 18 uint16_t f16; member 24 uint16_t f16; member 30 uint16_t f16; member 38 uint16_t f16; member 43 uint16_t f16; member 67 A->f16 = 4; in g2() 91 B->a.f16 = 4; in g4() 139 S->f16 = 4; in g8() 163 S2->f16 = 4; in g10()
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H A D | tbaa-class.cpp | 12 uint16_t f16; member in StructA 20 uint16_t f16; member in StructB 27 uint16_t f16; member in StructC 34 uint16_t f16; member in StructD 43 uint16_t f16; member in StructS 73 A->f16 = 4; in g2() 97 B->a.f16 = 4; in g4() 145 S->f16 = 4; in g8()
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/minix/external/bsd/llvm/dist/llvm/test/MC/ARM/ |
H A D | fp-armv8.s | 5 vcvtt.f64.f16 d3, s1 6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee] 7 vcvtt.f16.f64 s5, d12 8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee] 10 vcvtb.f64.f16 d3, s1 11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee] 12 vcvtb.f16.f64 s4, d1 15 vcvttge.f64.f16 d3, s1 17 vcvttgt.f16.f64 s5, d12 20 vcvtbeq.f64.f16 d3, s1 [all …]
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H A D | thumb-fp-armv8.s | 5 vcvtt.f64.f16 d3, s1 6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b] 7 vcvtt.f16.f64 s5, d12 8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b] 10 vcvtb.f64.f16 d3, s1 11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b] 12 vcvtb.f16.f64 s4, d1 16 vcvttge.f64.f16 d3, s1 19 vcvttgt.f16.f64 s5, d12 22 vcvtbeq.f64.f16 d3, s1 [all …]
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H A D | invalid-fp-armv8.s | 5 vcvtt.f64.f16 d3, s1 6 @ V7-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee] 7 vcvtt.f16.f64 s5, d12 8 @ V7-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee] 68 vcvtbgt.f64.f16 q0, d3 70 vcvttlt.f64.f16 s0, s3 72 vcvttvs.f16.f64 s0, s3 74 vcvtthi.f16.f64 q0, d3
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H A D | neont2-convert-encoding.s | 37 @ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0xf6,0xff,0x20,0x07] 38 vcvt.f32.f16 q8, d16 39 @ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x06] 40 vcvt.f16.f32 d16, q8
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H A D | neon-convert-encoding.s | 51 @ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0x20,0x07,0xf6,0xf3] 52 vcvt.f32.f16 q8, d16 53 @ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0x20,0x06,0xf6,0xf3] 54 vcvt.f16.f32 d16, q8
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/ |
H A D | fp16.ll | 23 ; CHECK-FP16: vcvtb.f32.f16 24 ; CHECK-ARMv8: vcvtb.f32.f16 28 ; CHECK-FP16: vcvtb.f32.f16 29 ; CHECK-ARMV8: vcvtb.f32.f16 34 ; CHECK-FP16: vcvtb.f16.f32 35 ; CHECK-ARMV8: vcvtb.f16.f32 52 ; CHECK-FP16: vcvtb.f32.f16 [[TMP32:s[0-9]+]], [[TMP16]] 56 ; CHECK-ARMV8: vcvtb.f64.f16 d0, [[TMP]] 73 ; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0
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H A D | half.ll | 34 ; CHECK-F16: vcvtb.f32.f16 35 ; CHECK-V8: vcvtb.f32.f16 46 ; CHECK-F16: vcvtb.f32.f16 48 ; CHECK-V8: vcvtb.f64.f16 58 ; CHECK-F16: vcvtb.f16.f32 59 ; CHECK-V8: vcvtb.f16.f32 70 ; CHECK-V8: vcvtb.f16.f64
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/minix/external/bsd/llvm/dist/clang/test/Sema/ |
H A D | variadic-promotion.c | 5 void test_floating_promotion(__fp16 *f16, float f32, double f64) { in test_floating_promotion() argument 6 variadic(3, *f16, f32, f64); in test_floating_promotion()
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/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/ARM/ |
H A D | fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1 7 # CHECK: vcvtt.f16.f64 s5, d12 10 # CHECK: vcvtb.f64.f16 d3, s1 13 # CHECK: vcvtb.f16.f64 s4, d1 16 # CHECK: vcvttge.f64.f16 d3, s1 19 # CHECK: vcvttgt.f16.f64 s5, d12 22 # CHECK: vcvtbeq.f64.f16 d3, s1 25 # CHECK: vcvtblt.f16.f64 s4, d1
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H A D | thumb-fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1 7 # CHECK: vcvtt.f16.f64 s5, d12 10 # CHECK: vcvtb.f64.f16 d3, s1 13 # CHECK: vcvtb.f16.f64 s4, d1 17 # CHECK: vcvttge.f64.f16 d3, s1 21 # CHECK: vcvttgt.f16.f64 s5, d12 25 # CHECK: vcvtbeq.f64.f16 d3, s1 29 # CHECK: vcvtblt.f16.f64 s4, d1
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H A D | invalid-because-armv7.txt | 7 # Would be vcvtt.f64.f16 d3, s1 12 # Would be vcvtb.f16.f64 s4, d1 17 # Would be vcvtblt.f16.f64 s4, d1
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/minix/external/bsd/llvm/dist/llvm/test/tools/llvm-objdump/ARM/ |
H A D | macho-mattr-arm.test | 3 vcvtt.f64.f16 d3, s1 5 @ CHECK: e0 3b b2 ee vcvtt.f64.f16 d3, s1
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/NVPTX/ |
H A D | fp16.ll | 9 ; CHECK: cvt.f32.f16 19 ; CHECK: cvt.f64.f16 29 ; CHECK: cvt.rn.f16.f32 39 ; CHECK: cvt.rn.f16.f64
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H A D | half.ll | 34 ; CHECK: cvt.f32.f16 44 ; CHECK: cvt.f64.f16 54 ; CHECK: cvt.rn.f16.f32 64 ; CHECK: cvt.rn.f16.f64
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/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/Mips/mips64r2/ |
H A D | valid-xfail-mips64r2.txt | 11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 42 0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16 46 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2 53 0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16 57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra 59 0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16 63 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 64 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
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/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/Mips/mips32r2/ |
H A D | valid-xfail-mips32r2.txt | 11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 42 0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16 46 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2 51 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 59 0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16 63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra 64 0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16 67 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
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/minix/external/bsd/llvm/dist/clang/test/CXX/except/except.spec/ |
H A D | p5-virtual.cpp | 46 virtual void f16(); 82 virtual void f16() throw();
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/minix/common/lib/libc/arch/sparc64/string/ |
H A D | memcpy.S | 787 ldda [%o0] ASI_BLK_P, %f16 811 faligndata %f14, %f16, %f32 813 faligndata %f16, %f18, %f34 884 ldda [%o0] ASI_BLK_P, %f16 906 faligndata %f16, %f18, %f32 938 ldda [%o0] ASI_BLK_P, %f16 980 ldda [%o0] ASI_BLK_P, %f16 996 faligndata %f14, %f16, %f44 1034 ldda [%o0] ASI_BLK_P, %f16 1074 ldda [%o0] ASI_BLK_P, %f16 [all …]
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/minix/external/bsd/llvm/dist/llvm/test/Analysis/TypeBasedAliasAnalysis/ |
H A D | tbaa-path.ll | 40 ; Access to i32* and &(A->f16). 57 %f16 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 0 58 store i16 4, i16* %f16, align 2, !tbaa !11 95 ; Access to &(A->f32) and &(B->a.f16). 114 %f16 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 0 115 store i16 4, i16* %f16, align 2, !tbaa !14 209 ; Access to &(A->f32) and &(S->f16). 227 %f16 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 0 228 store i16 4, i16* %f16, align 2, !tbaa !19 265 ; Access to &(S->f32) and &(S2->f16). [all …]
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/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/Mips/mips4/ |
H A D | valid-xfail-mips4.txt | 11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 34 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 37 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
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/minix/external/bsd/llvm/dist/llvm/test/MC/Mips/mips1/ |
H A D | valid.s | 7 abs.s $f9,$f16 28 c.ngle.d $f0,$f16 51 lwc1 $f16,10225($k0) 68 mul.d $f20,$f20,$f16
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/minix/external/bsd/llvm/dist/llvm/test/MC/Mips/mips32r6/ |
H A D | invalid-mips32r2.s | 11 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 14 …nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/minix/external/bsd/llvm/dist/llvm/test/MC/Mips/mips32r2/ |
H A D | valid.s | 7 abs.s $f9,$f16 45 c.ngle.d $f0,$f16 90 lwc1 $f16,10225($k0) 125 msub.s $f12,$f19,$f10,$f16 129 mthc1 $zero,$f16 134 mul.d $f20,$f20,$f16 146 nmsub.d $f30,$f8,$f16,$f30
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