Home
last modified time | relevance | path

Searched refs:isUse (Results 1 – 25 of 55) sorted by relevance

123

/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DProcessImplicitDefs.cpp72 if (MO->isReg() && MO->isUse() && MO->readsReg()) in canTurnIntoImplicitDef()
112 if (MO->isUse()) in processImplicitDef()
H A DExpandPostRAPseudos.cpp74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
H A DMachineInstr.cpp325 if (isUndef() && isUse()) { in print()
771 if (NewMO->isUse()) { in addOperand()
1142 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1174 if (MO.isUse()) in readsWritesVirtualRegister()
1254 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1286 if (MO.isUse()) in findTiedOperandIdx()
1291 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1335 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1500 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
1777 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) in addRegisterKilled()
[all …]
H A DRegisterScavenging.cpp134 if (MO.isUse()) { in determineKillsAndDefs()
205 if (MO.isUse()) { in forward()
377 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
H A DLivePhysRegs.cpp79 assert(O->isUse()); in stepForward()
H A DTwoAddressInstructionPass.cpp202 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction()
327 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
1000 if (MO.isUse()) { in rescheduleKillAboveMI()
1041 if (MO.isUse()) { in rescheduleKillAboveMI()
1246 if (MO.isUse()) { in tryInstructionTransform()
1326 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1439 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1467 MO.isUse()) { in processTiedPairs()
1504 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
H A DRegAllocFast.cpp236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
614 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
646 if (MO.isUse()) in reloadVirtReg()
746 if (MO.isUse()) { in handleThroughOperands()
933 if (MO.isUse()) { in AllocateBasicBlock()
945 if (MO.isUse()) { in AllocateBasicBlock()
981 if (MO.isUse()) { in AllocateBasicBlock()
H A DMachineSink.cpp354 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
538 if (MO.isUse()) { in FindSuccToSinkTo()
550 if (MO.isUse()) continue; in FindSuccToSinkTo()
H A DCriticalAntiDepBreaker.cpp228 if (MO.isUse() && Special) { in PrescanInstruction()
292 if (!MO.isUse()) continue; in ScanInstruction()
603 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
H A DDeadMachineInstructionElim.cpp163 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
H A DMachineCSE.cpp126 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
196 if (MO.isUse()) in isPhysDefTriviallyDead()
402 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
H A DLiveIntervalAnalysis.cpp723 if (MO.isUse()) { in addKillFlags()
797 LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
802 return (isDef + isUse) * (Freq.getFrequency() * Scale); in getSpillWeight()
923 if (MO->isUse()) in updateAllRanges()
1018 if (MO->isReg() && MO->isUse()) in handleMoveDown()
1315 } else if (MO.isUse()) { in repairOldRegInRange()
H A DTargetInstrInfo.cpp527 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); in foldMemoryOperand()
619 if (MO.isUse()) { in isReallyTriviallyReMaterializableGeneric()
640 if (MO.isUse()) in isReallyTriviallyReMaterializableGeneric()
H A DBranchFolding.cpp167 if (!MO.isReg() || !MO.isUse()) in OptimizeImpDefsBlock()
1569 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1603 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps()
1637 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1768 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
H A DInlineSpiller.cpp874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
925 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
1137 if (MO->isUse()) in foldMemoryOperand()
1309 if (MO.isUse()) { in spillAroundUses()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp265 if (MO.isUse()) { in delayHasHazard()
290 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
297 assert(RegOrImm.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
318 if (MO.isUse()) { in insertDefsUses()
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIInsertWaits.cpp220 if (I->isReg() && I->isUse()) in isOpRelevant()
305 if (Op.isUse()) in pushInstruction()
405 if (Op.isUse()) in handleOperands()
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h799 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
814 if (Op->isUse()) in advance()
902 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
917 if (Op->isUse()) in advance()
H A DMachineOperand.h274 bool isUse() const { in isUse() function
333 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
H A DLiveIntervalAnalysis.h103 static float getSpillWeight(bool isDef, bool isUse,
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
571 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
578 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
H A DHexagonVLIWPacketizer.cpp355 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { in IsCallDependent()
489 MI->getOperand(opNum).isUse()) { in GetPostIncrementOperand()
847 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp110 if (!MO.isReg() || !MO.isUse() || in getCallTargetRegOpnd()
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp70 if (MO.isUse()) in TrackDefUses()
H A DA15SDOptimizer.cpp196 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses()
413 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()

123