/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
H A D | ProcessImplicitDefs.cpp | 72 if (MO->isReg() && MO->isUse() && MO->readsReg()) in canTurnIntoImplicitDef() 112 if (MO->isUse()) in processImplicitDef()
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H A D | ExpandPostRAPseudos.cpp | 74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs() 84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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H A D | MachineInstr.cpp | 325 if (isUndef() && isUse()) { in print() 771 if (NewMO->isUse()) { in addOperand() 1142 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx() 1174 if (MO.isUse()) in readsWritesVirtualRegister() 1254 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands() 1286 if (MO.isUse()) in findTiedOperandIdx() 1291 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx() 1335 if (MO.isReg() && MO.isUse()) in clearKillInfo() 1500 if (!MO.isReg() || MO.isUse()) in allDefsAreDead() 1777 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) in addRegisterKilled() [all …]
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H A D | RegisterScavenging.cpp | 134 if (MO.isUse()) { in determineKillsAndDefs() 205 if (MO.isUse()) { in forward() 377 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
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H A D | LivePhysRegs.cpp | 79 assert(O->isUse()); in stepForward()
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H A D | TwoAddressInstructionPass.cpp | 202 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction() 327 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef() 438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse() 1000 if (MO.isUse()) { in rescheduleKillAboveMI() 1041 if (MO.isUse()) { in rescheduleKillAboveMI() 1246 if (MO.isUse()) { in tryInstructionTransform() 1326 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands() 1439 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs() 1467 MO.isUse()) { in processTiedPairs() 1504 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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H A D | RegAllocFast.cpp | 236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag() 614 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg() 646 if (MO.isUse()) in reloadVirtReg() 746 if (MO.isUse()) { in handleThroughOperands() 933 if (MO.isUse()) { in AllocateBasicBlock() 945 if (MO.isUse()) { in AllocateBasicBlock() 981 if (MO.isUse()) { in AllocateBasicBlock()
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H A D | MachineSink.cpp | 354 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge() 538 if (MO.isUse()) { in FindSuccToSinkTo() 550 if (MO.isUse()) continue; in FindSuccToSinkTo()
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H A D | CriticalAntiDepBreaker.cpp | 228 if (MO.isUse() && Special) { in PrescanInstruction() 292 if (!MO.isUse()) continue; in ScanInstruction() 603 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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H A D | DeadMachineInstructionElim.cpp | 163 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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H A D | MachineCSE.cpp | 126 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY() 196 if (MO.isUse()) in isPhysDefTriviallyDead() 402 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
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H A D | LiveIntervalAnalysis.cpp | 723 if (MO.isUse()) { in addKillFlags() 797 LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument 802 return (isDef + isUse) * (Freq.getFrequency() * Scale); in getSpillWeight() 923 if (MO->isUse()) in updateAllRanges() 1018 if (MO->isReg() && MO->isUse()) in handleMoveDown() 1315 } else if (MO.isUse()) { in repairOldRegInRange()
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H A D | TargetInstrInfo.cpp | 527 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); in foldMemoryOperand() 619 if (MO.isUse()) { in isReallyTriviallyReMaterializableGeneric() 640 if (MO.isUse()) in isReallyTriviallyReMaterializableGeneric()
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H A D | BranchFolding.cpp | 167 if (!MO.isReg() || !MO.isUse()) in OptimizeImpDefsBlock() 1569 if (MO.isUse()) { in findHoistingInsertPosAndDeps() 1603 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps() 1637 if (MO.isUse()) { in findHoistingInsertPosAndDeps() 1768 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
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H A D | InlineSpiller.cpp | 874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor() 925 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor() 1137 if (MO->isUse()) in foldMemoryOperand() 1309 if (MO.isUse()) { in spillAroundUses()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 265 if (MO.isUse()) { in delayHasHazard() 290 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses() 297 assert(RegOrImm.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses() 318 if (MO.isUse()) { in insertDefsUses()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | SIInsertWaits.cpp | 220 if (I->isReg() && I->isUse()) in isOpRelevant() 305 if (Op.isUse()) in pushInstruction() 405 if (Op.isUse()) in handleOperands()
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/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 799 if ((!ReturnUses && op->isUse()) || in defusechain_iterator() 814 if (Op->isUse()) in advance() 902 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator() 917 if (Op->isUse()) in advance()
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H A D | MachineOperand.h | 274 bool isUse() const { in isUse() function 333 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
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H A D | LiveIntervalAnalysis.h | 103 static float getSpillWeight(bool isDef, bool isUse,
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonNewValueJump.cpp | 150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY() 571 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction() 578 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
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H A D | HexagonVLIWPacketizer.cpp | 355 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { in IsCallDependent() 489 MI->getOperand(opNum).isUse()) { in GetPostIncrementOperand() 847 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 110 if (!MO.isReg() || !MO.isUse() || in getCallTargetRegOpnd()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 70 if (MO.isUse()) in TrackDefUses()
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H A D | A15SDOptimizer.cpp | 196 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses() 413 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()
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