| /netbsd/external/gpl3/gdb/dist/sim/testsuite/sim/bfin/ |
| H A D | c_dsp32shiftim_a0alr.s | 24 A0 = A0 << 0; /* a0 = 0x00000000 */ define
31 A0 = A0 << 1; /* a0 = 0x00000000 */ define
38 A0 = A0 << 15; /* a0 = 0x00000000 */ define
45 A0 = A0 << 31; /* a0 = 0x00000000 */ define
52 A0 = A0 >>> 1; /* a0 = 0x00000000 */ define
60 A0 = A0 >>> 16; /* a0 = 0x00000000 */ define
67 A0 = A0 >>> 31; /* a0 = 0x00000000 */ define
92 A0 = A0 << 0; /* a0 = 0x00000000 */ define
99 A0 = A0 << 3; /* a0 = 0x00000000 */ define
106 A0 = A0 << 15; /* a0 = 0x00000000 */ define
[all …]
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| H A D | c_dsp32shift_a0alr.s | 21 A0 = 0; define
24 A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */ define
31 A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */ define
38 A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */ define
45 A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */ define
52 A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */ define
57 A0 = 0; define
60 A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */ define
67 A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */ define
74 A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */ define
[all …]
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| H A D | s21.s | 21 A0 = ROT A0 BY 1; define
41 A0 = ROT A0 BY 1; define
61 A0 = ROT A0 BY 1; define
81 A0 = ROT A0 BY 2; define
100 A0 = ROT A0 BY 3; define
120 A0 = ROT A0 BY 31; define
140 A0 = ROT A0 BY -1; define
160 A0 = ROT A0 BY -1; define
180 A0 = ROT A0 BY -2; define
200 A0 = ROT A0 BY -9; define
[all …]
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| H A D | s30.s | 12 A0.w = R0;
14 A0.x = R0;
18 A0 = ASHIFT A0 BY R5.L; define
19 _DBG A0;
36 A0 = ASHIFT A0 BY R5.L; define
54 A0 = ASHIFT A0 BY R5.L; define
72 A0 = ASHIFT A0 BY R5.L; define
90 A0 = ASHIFT A0 BY R5.L; define
108 A0 = ASHIFT A0 BY R5.L; define
126 A0 = ASHIFT A0 BY R5.L; define
[all …]
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| H A D | c_dsp32shift_bitmux.s | 9 A0 = 0; define
35 R0 = A0.w;
36 R1 = A0.x;
65 R0 = A0.w;
66 R1 = A0.x;
95 R0 = A0.w;
96 R1 = A0.x;
125 R0 = A0.w;
126 R1 = A0.x;
155 R0 = A0.w;
[all …]
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| H A D | random_0013.S | 24 R3.L = A0 (IH);
32 R4.L = A0 (IH);
40 R6.L = A0 (IH);
48 R4.L = A0 (IH);
56 R3.L = A0 (IH);
87 R3.L = A0 (IH);
106 R3.L = A0 (IH);
114 R2.L = A0 (IH);
122 R2.L = A0 (IH);
130 R4.L = A0 (IH);
[all …]
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| H A D | c_dsp32shift_bxor.s | 10 A0 = R1; define
72 R2.L = CC = BXOR( A0 , R0 );
73 R3.L = CC = BXOR( A0 , R1 );
99 A0 = BXORSHIFT( A0 , A1, CC ); define
101 A0 = BXORSHIFT( A0 , A1, CC ); define
103 A0 = BXORSHIFT( A0 , A1, CC ); define
105 A0 = BXORSHIFT( A0 , A1, CC ); define
107 A0 = BXORSHIFT( A0 , A1, CC ); define
109 A0 = BXORSHIFT( A0 , A1, CC ); define
111 A0 = BXORSHIFT( A0 , A1, CC ); define
[all …]
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| H A D | c_dsp32alu_rrpm_aa.s | 23 R0 = A1 + A0, R7 = A1 - A0 (NS);
24 R1 = A0 + A1, R6 = A0 - A1 (NS);
25 R2 = A1 + A0, R5 = A1 - A0 (NS);
26 R3 = A0 + A1, R4 = A0 - A1 (NS);
27 R4 = A1 + A0, R0 = A1 - A0 (NS);
28 R5 = A0 + A1, R1 = A0 - A1 (NS);
29 R6 = A0 + A1, R2 = A0 - A1 (NS);
30 R7 = A1 + A0, R3 = A1 - A0 (NS);
50 R3 = A1 + A0, R7 = A1 - A0 (S);
51 R4 = A0 + A1, R6 = A0 - A1 (S);
[all …]
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| H A D | add_sub_acc.s | 7 A1 = A0 = 0;
10 A0.w = R0;
12 A0.x = R0;
15 _DBG A0;
18 A0 -= A1;
19 _dbg A0;
33 _DBG A0;
36 A0 -= A1;
37 _dbg A0;
52 _DBG A0;
[all …]
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| H A D | c_dsp32mac_a1a0_iuw32.s | 12 A0 = 0; define
27 R0 = A0.w;
30 R6 = A0.w;
33 R2 = A0.w;
36 R5 = A0.w;
56 R2 = A0.w;
59 R6 = A0.w;
62 R0 = A0.w;
65 R4 = A0.w;
85 R4 = A0.w;
[all …]
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| H A D | a22.s | 9 A0.w = R0;
11 A0.x = R0;
12 A0 = - A0; define
13 _DBG A0;
14 R4 = A0.w;
15 R5 = A0.x;
23 A0 = - A0; define
26 _DBG A0;
34 A0 = - A0; define
44 A0 = - A0; define
[all …]
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| /netbsd/external/gpl3/gdb.old/dist/sim/testsuite/sim/bfin/ |
| H A D | c_dsp32shiftim_a0alr.s | 24 A0 = A0 << 0; /* a0 = 0x00000000 */ define
31 A0 = A0 << 1; /* a0 = 0x00000000 */ define
38 A0 = A0 << 15; /* a0 = 0x00000000 */ define
45 A0 = A0 << 31; /* a0 = 0x00000000 */ define
52 A0 = A0 >>> 1; /* a0 = 0x00000000 */ define
60 A0 = A0 >>> 16; /* a0 = 0x00000000 */ define
67 A0 = A0 >>> 31; /* a0 = 0x00000000 */ define
92 A0 = A0 << 0; /* a0 = 0x00000000 */ define
99 A0 = A0 << 3; /* a0 = 0x00000000 */ define
106 A0 = A0 << 15; /* a0 = 0x00000000 */ define
[all …]
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| H A D | c_dsp32shift_a0alr.s | 21 A0 = 0; define
24 A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */ define
31 A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */ define
38 A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */ define
45 A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */ define
52 A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */ define
57 A0 = 0; define
60 A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */ define
67 A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */ define
74 A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */ define
[all …]
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| H A D | s21.s | 21 A0 = ROT A0 BY 1; define
41 A0 = ROT A0 BY 1; define
61 A0 = ROT A0 BY 1; define
81 A0 = ROT A0 BY 2; define
100 A0 = ROT A0 BY 3; define
120 A0 = ROT A0 BY 31; define
140 A0 = ROT A0 BY -1; define
160 A0 = ROT A0 BY -1; define
180 A0 = ROT A0 BY -2; define
200 A0 = ROT A0 BY -9; define
[all …]
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| H A D | s30.s | 12 A0.w = R0;
14 A0.x = R0;
18 A0 = ASHIFT A0 BY R5.L; define
19 _DBG A0;
36 A0 = ASHIFT A0 BY R5.L; define
54 A0 = ASHIFT A0 BY R5.L; define
72 A0 = ASHIFT A0 BY R5.L; define
90 A0 = ASHIFT A0 BY R5.L; define
108 A0 = ASHIFT A0 BY R5.L; define
126 A0 = ASHIFT A0 BY R5.L; define
[all …]
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| H A D | c_dsp32shift_bitmux.s | 9 A0 = 0; define
35 R0 = A0.w;
36 R1 = A0.x;
65 R0 = A0.w;
66 R1 = A0.x;
95 R0 = A0.w;
96 R1 = A0.x;
125 R0 = A0.w;
126 R1 = A0.x;
155 R0 = A0.w;
[all …]
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| H A D | random_0013.S | 24 R3.L = A0 (IH);
32 R4.L = A0 (IH);
40 R6.L = A0 (IH);
48 R4.L = A0 (IH);
56 R3.L = A0 (IH);
87 R3.L = A0 (IH);
106 R3.L = A0 (IH);
114 R2.L = A0 (IH);
122 R2.L = A0 (IH);
130 R4.L = A0 (IH);
[all …]
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| H A D | c_dsp32shift_bxor.s | 10 A0 = R1; define
72 R2.L = CC = BXOR( A0 , R0 );
73 R3.L = CC = BXOR( A0 , R1 );
99 A0 = BXORSHIFT( A0 , A1, CC ); define
101 A0 = BXORSHIFT( A0 , A1, CC ); define
103 A0 = BXORSHIFT( A0 , A1, CC ); define
105 A0 = BXORSHIFT( A0 , A1, CC ); define
107 A0 = BXORSHIFT( A0 , A1, CC ); define
109 A0 = BXORSHIFT( A0 , A1, CC ); define
111 A0 = BXORSHIFT( A0 , A1, CC ); define
[all …]
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| H A D | c_dsp32alu_rrpm_aa.s | 23 R0 = A1 + A0, R7 = A1 - A0 (NS);
24 R1 = A0 + A1, R6 = A0 - A1 (NS);
25 R2 = A1 + A0, R5 = A1 - A0 (NS);
26 R3 = A0 + A1, R4 = A0 - A1 (NS);
27 R4 = A1 + A0, R0 = A1 - A0 (NS);
28 R5 = A0 + A1, R1 = A0 - A1 (NS);
29 R6 = A0 + A1, R2 = A0 - A1 (NS);
30 R7 = A1 + A0, R3 = A1 - A0 (NS);
50 R3 = A1 + A0, R7 = A1 - A0 (S);
51 R4 = A0 + A1, R6 = A0 - A1 (S);
[all …]
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| H A D | add_sub_acc.s | 7 A1 = A0 = 0;
10 A0.w = R0;
12 A0.x = R0;
15 _DBG A0;
18 A0 -= A1;
19 _dbg A0;
33 _DBG A0;
36 A0 -= A1;
37 _dbg A0;
52 _DBG A0;
[all …]
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| H A D | c_dsp32mac_a1a0_iuw32.s | 12 A0 = 0; define
27 R0 = A0.w;
30 R6 = A0.w;
33 R2 = A0.w;
36 R5 = A0.w;
56 R2 = A0.w;
59 R6 = A0.w;
62 R0 = A0.w;
65 R4 = A0.w;
85 R4 = A0.w;
[all …]
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| /netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/bfin/ |
| H A D | move2.s | 28 A0.X = A0.X;
29 A0.W = A0.W;
36 R2 = A0.W;
37 R3 = A0.X;
52 A0.X = R3;
53 A0.W = R2;
57 A0.X = A0.W;
65 A0.W = A0.W;
111 A0.X = I0;
112 A0.W = I1;
[all …]
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| /netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/bfin/ |
| H A D | move2.s | 28 A0.X = A0.X;
29 A0.W = A0.W;
36 R2 = A0.W;
37 R3 = A0.X;
52 A0.X = R3;
53 A0.W = R2;
57 A0.X = A0.W;
65 A0.W = A0.W;
111 A0.X = I0;
112 A0.W = I1;
[all …]
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| /netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/metag/ |
| H A D | metacore12.s | 1015 ANDLE A0.2,D0.7,A0.7
1136 ANDLE A0.2,D1.7,A0.7
3559 ADDNV PC,A0.7,A0.7
3642 ADDNV RA,A0.7,A0.7
3883 NEG A0.7,A0.7
3925 SUBNV PC,A0.7,A0.7
5707 GETB A0.7,[A0.7+A0.7]
5791 GETW A0.7,[A0.7+A0.7]
6097 GETD A0.7,[A0.7+A0.7]
6187 GETL A0.7,A1.7,[A0.7+A0.7]
[all …]
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| /netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/metag/ |
| H A D | metacore12.s | 1015 ANDLE A0.2,D0.7,A0.7
1136 ANDLE A0.2,D1.7,A0.7
3559 ADDNV PC,A0.7,A0.7
3642 ADDNV RA,A0.7,A0.7
3883 NEG A0.7,A0.7
3925 SUBNV PC,A0.7,A0.7
5707 GETB A0.7,[A0.7+A0.7]
5791 GETW A0.7,[A0.7+A0.7]
6097 GETD A0.7,[A0.7+A0.7]
6187 GETL A0.7,A1.7,[A0.7+A0.7]
[all …]
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