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Searched refs:AMDGPU (Results 1 – 25 of 212) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp127 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
133 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
183 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass; in prepare()
440 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); in reservedPrivateSegmentBufferReg()
991 AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 && in getFlatScratchSpillOpcode()
992 AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0; in getFlatScratchSpillOpcode()
1125 assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 in buildSpillLoadStore()
1653 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr)); in eliminateFrameIndex()
1683 unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
2357 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
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H A DSIOptimizeExecMasking.cpp57 case AMDGPU::COPY: in isCopyFromExec()
58 case AMDGPU::S_MOV_B64: in isCopyFromExec()
60 case AMDGPU::S_MOV_B32: in isCopyFromExec()
64 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
75 case AMDGPU::COPY: in isCopyToExec()
80 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
98 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
114 case AMDGPU::S_OR_B32: in isLogicalOpOnExec()
179 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
184 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
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H A DAMDGPURegisterBankInfo.cpp341 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsic()
344 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsic()
353 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
356 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
359 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
362 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
403 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
406 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
722 AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in executeInWaterfallLoop()
724 AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in executeInWaterfallLoop()
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H A DSIInstrInfo.cpp2576 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
2577 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in insertSelect()
2578 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in insertSelect()
2579 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, in insertSelect()
2583 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, in insertSelect()
2584 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, in insertSelect()
2585 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11, in insertSelect()
2586 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15, in insertSelect()
4354 case AMDGPU::COPY: return AMDGPU::COPY; in getVALUOp()
4355 case AMDGPU::PHI: return AMDGPU::PHI; in getVALUOp()
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H A DSIPeepholeSDWA.cpp485 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
856 assert((Opc == AMDGPU::V_ADD_CO_U32_e64 || Opc == AMDGPU::V_SUB_CO_U32_e64) && in pseudoOpConvertToVOP2()
991 SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(Opcode)); in convertToSDWA()
1005 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst) != -1); in convertToSDWA()
1009 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
1012 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
1021 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0) != -1 && in convertToSDWA()
1033 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1) != -1 && in convertToSDWA()
1053 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::clamp) != -1); in convertToSDWA()
1062 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::omod) != -1) { in convertToSDWA()
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H A DGCNDPPCombine.cpp166 case AMDGPU::IMPLICIT_DEF: in getOldOpndValue()
168 case AMDGPU::COPY: in getOldOpndValue()
169 case AMDGPU::V_MOV_B32_e32: in getOldOpndValue()
206 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
299 case AMDGPU::V_ADD_U32_e32: in isIdentityValue()
300 case AMDGPU::V_ADD_U32_e64: in isIdentityValue()
303 case AMDGPU::V_OR_B32_e32: in isIdentityValue()
304 case AMDGPU::V_OR_B32_e64: in isIdentityValue()
309 case AMDGPU::V_MAX_U32_e32: in isIdentityValue()
310 case AMDGPU::V_MAX_U32_e64: in isIdentityValue()
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H A DSIFoldOperands.cpp162 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in isInlineConstantIfFolded()
219 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) in updateOperand()
848 AMDGPU::getNamedOperandIdx(UseOpc, AMDGPU::OpName::src0))) { in foldOperand()
1007 return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpc()
1053 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in tryConstantFoldOp()
1058 if ((Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 || in tryConstantFoldOp()
1066 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in tryConstantFoldOp()
1168 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); in tryFoldCndMask()
1170 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in tryFoldCndMask()
1178 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in tryFoldCndMask()
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H A DAMDGPUInstructionSelector.cpp269 return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32; in getLogicalBitOpcode()
271 return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32; in getLogicalBitOpcode()
273 return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32; in getLogicalBitOpcode()
427 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC) in selectG_UADDO_USUBO_UADDE_USUBE()
781 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectInterpP1F16()
1161 AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in selectGroupStaticSize()
1278 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectDSOrderedIntrinsic()
2042 AMDGPU::SReg_64RegClass : AMDGPU::SReg_32RegClass; in selectG_SZA_EXT()
2048 AMDGPU::S_SEXT_I32_I8 : AMDGPU::S_SEXT_I32_I16; in selectG_SZA_EXT()
2146 &AMDGPU::SReg_32RegClass : &AMDGPU::VGPR_32RegClass; in selectG_CONSTANT()
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H A DSILoadStoreOptimizer.cpp403 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
449 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
544 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
547 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
550 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in setMI()
553 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset); in setMI()
556 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in setMI()
559 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::ssamp); in setMI()
1554 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1555 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, 0}, in getSubRegIdxs()
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H A DGCNHazardRecognizer.cpp71 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; in isRWLane()
115 case AMDGPU::S_SENDMSG: in isSendMsgTraceDataOrGDS()
120 case AMDGPU::DS_NOP: in isSendMsgTraceDataOrGDS()
886 Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa; in fixVcmpxPermlaneHazards()
973 const AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU()); in fixSMEMtoVectorWriteHazards()
1008 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); in fixSMEMtoVectorWriteHazards()
1033 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) in fixSMEMtoVectorWriteHazards()
1152 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(I.getOpcode()); in checkNSAtoVMEMHazard()
1275 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards908()
1395 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards90A()
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H A DSIShrinkInstructions.cpp66 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
192 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) { in shrinkScalarCompare()
197 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32; in shrinkScalarCompare()
216 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in shrinkMIMG()
225 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in shrinkMIMG()
266 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
287 AMDGPU::getMIMGOpcode(Info->BaseOpcode, AMDGPU::MIMGEncGfx10Default, in shrinkMIMG()
299 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata), in shrinkMIMG()
352 if ((Opc == AMDGPU::S_ANDN2_B32 || Opc == AMDGPU::S_ORN2_B32) && in shrinkScalarLogicOp()
601 unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
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H A DAMDGPUArgumentUsageInfo.cpp99 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
103 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
113 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
116 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
120 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
130 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
134 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
154 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
162 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
163 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
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H A DAMDGPUAsmPrinter.cpp40 using namespace llvm::AMDGPU;
354 if ((AMDGPU::isGFX10Plus(STI) || AMDGPU::isGFX90A(STI)) && in doFinalization()
816 case AMDGPU::EXEC: in analyzeResourceUsage()
819 case AMDGPU::SCC: in analyzeResourceUsage()
820 case AMDGPU::M0: in analyzeResourceUsage()
826 case AMDGPU::MODE: in analyzeResourceUsage()
836 case AMDGPU::VCC: in analyzeResourceUsage()
837 case AMDGPU::VCC_LO: in analyzeResourceUsage()
838 case AMDGPU::VCC_HI: in analyzeResourceUsage()
859 case AMDGPU::TBA: in analyzeResourceUsage()
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H A DSIInsertWaitcnts.cpp159 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); in getVmemType()
361 AMDGPU::IsaVersion IV;
525 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr); in updateByEvent()
568 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
828 AMDGPU::Waitcnt OldWait = AMDGPU::decodeWaitcnt(IV, IEnc); in applyPreexistingWaitcnt()
909 return (Opc == AMDGPU::S_CBRANCH_VCCNZ || Opc == AMDGPU::S_CBRANCH_VCCZ) && in readsVCCZ()
946 AMDGPU::Waitcnt Wait; in generateWaitcntInstBefore()
1053 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in generateWaitcntInstBefore()
1065 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in generateWaitcntInstBefore()
1349 if (Imm >= AMDGPU::Exp::ET_PARAM0 && Imm <= AMDGPU::Exp::ET_PARAM31) in updateEventWaitcntAfter()
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H A DSIOptimizeExecMaskingPreRA.cpp315 AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in runOnMachineFunction()
316 Andn2Opc = Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64; in runOnMachineFunction()
318 Wave32 ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in runOnMachineFunction()
319 XorTermrOpc = Wave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term; in runOnMachineFunction()
320 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC); in runOnMachineFunction()
321 ExecReg = MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC); in runOnMachineFunction()
323 DenseSet<Register> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI}); in runOnMachineFunction()
329 RecalcRegs.insert(AMDGPU::SCC); in runOnMachineFunction()
335 RecalcRegs.insert(AMDGPU::VCC_LO); in runOnMachineFunction()
336 RecalcRegs.insert(AMDGPU::VCC_HI); in runOnMachineFunction()
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H A DSILowerControlFlow.cpp587 case AMDGPU::SI_IF: in process()
591 case AMDGPU::SI_ELSE: in process()
599 case AMDGPU::SI_LOOP: in process()
603 case AMDGPU::SI_END_CF: in process()
618 case AMDGPU::S_OR_B64: in process()
620 case AMDGPU::S_OR_B32: in process()
642 TII->get(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), Exec) in lowerInitExec()
687 TII->get(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), Exec) in lowerInitExec()
695 TII->get(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64), in lowerInitExec()
801 Exec = AMDGPU::EXEC; in runOnMachineFunction()
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H A DSIWholeQuadMode.cpp441 case AMDGPU::EXEC: in markOperand()
442 case AMDGPU::EXEC_LO: in markOperand()
564 if (Opcode == AMDGPU::SI_PS_LIVE || Opcode == AMDGPU::SI_LIVE_MASK) { in scanInstructions()
724 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC) in saveSCC()
746 case AMDGPU::S_AND_B32: in splitBlock()
749 case AMDGPU::S_AND_B64: in splitBlock()
752 case AMDGPU::S_MOV_B32: in splitBlock()
873 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
976 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1126 MO.getReg() == AMDGPU::EXEC_LO || MO.getReg() == AMDGPU::EXEC; in prepareInsertion()
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H A DSIFrameLowering.cpp292 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO) in emitEntryFunctionFlatScratchInit()
295 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI) in emitEntryFunctionFlatScratchInit()
305 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO) in emitEntryFunctionFlatScratchInit()
315 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI) in emitEntryFunctionFlatScratchInit()
485 assert(SPReg != AMDGPU::SP_REG); in emitEntryFunctionPrologue()
709 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in buildScratchExecCopy()
786 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitPrologue()
787 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
1089 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitEpilogue()
1090 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
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H A DR600RegisterInfo.td3 let Namespace = "AMDGPU";
16 let Namespace = "AMDGPU";
22 let Namespace = "AMDGPU";
31 let Namespace = "AMDGPU";
174 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
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H A DSIPreEmitPeephole.cpp82 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVccBranch()
83 const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in optimizeVccBranch()
84 const unsigned AndN2 = IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64; in optimizeVccBranch()
85 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVccBranch()
174 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
213 TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ : AMDGPU::S_CBRANCH_EXECNZ)); in optimizeVccBranch()
242 case AMDGPU::S_SET_GPR_IDX_MODE: in optimizeSetGPR()
244 case AMDGPU::S_SET_GPR_IDX_OFF: in optimizeSetGPR()
357 case AMDGPU::S_CBRANCH_VCCZ: in runOnMachineFunction()
358 case AMDGPU::S_CBRANCH_VCCNZ: in runOnMachineFunction()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2315 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2320 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
2330 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2335 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2340 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
3417 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3423 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGAddrSize()
3424 int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16); in validateMIMGAddrSize()
3500 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGMSAA()
3973 (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO); in validateVccOperand()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp234 case AMDGPU::OPERAND_REG_IMM_INT32: in getLitEncoding()
235 case AMDGPU::OPERAND_REG_IMM_FP32: in getLitEncoding()
246 case AMDGPU::OPERAND_REG_IMM_INT64: in getLitEncoding()
247 case AMDGPU::OPERAND_REG_IMM_FP64: in getLitEncoding()
253 case AMDGPU::OPERAND_REG_IMM_INT16: in getLitEncoding()
257 case AMDGPU::OPERAND_REG_IMM_FP16: in getLitEncoding()
287 using namespace AMDGPU::OpName; in getImplicitOpSelHiEncoding()
405 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
415 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { in getSDWASrcEncoding()
435 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
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H A DAMDGPUInstPrinter.cpp242 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
305 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
345 case AMDGPU::FP_REG: in printRegOperand()
346 case AMDGPU::SP_REG: in printRegOperand()
349 case AMDGPU::SCC: in printRegOperand()
410 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
580 AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI); in printDefaultVccOperand()
722 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printOperand()
992 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
995 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp278 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; in IsAGPROperand()
301 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeOperand_AVLdSt_Any()
307 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); in decodeOperand_AVLdSt_Any()
568 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in getInstruction()
579 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); in getInstruction()
591 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); in getInstruction()
687 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in convertMIMGInst()
708 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in convertMIMGInst()
717 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); in convertMIMGInst()
719 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); in convertMIMGInst()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp89 namespace AMDGPU { namespace
826 if (AMDGPU::isGFX90A(*STI)) { in getDefaultAmdhsaKernelDescriptor()
1470 Reg == AMDGPU::SCC; in isSGPR()
1481 using namespace AMDGPU; \
1602 case AMDGPU::VS_32RegClassID: in getRegBitWidth()
1603 case AMDGPU::AV_32RegClassID: in getRegBitWidth()
1609 case AMDGPU::VS_64RegClassID: in getRegBitWidth()
1610 case AMDGPU::AV_64RegClassID: in getRegBitWidth()
1624 case AMDGPU::AV_96RegClassID: in getRegBitWidth()
1632 case AMDGPU::AV_128RegClassID: in getRegBitWidth()
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