| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 150 const MachineOperand *BaseOp; in runOnMachineFunction() local
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
155 BaseOp->isReg()) { in runOnMachineFunction()
156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
|
| H A D | AArch64InstrInfo.h | 137 const MachineOperand *&BaseOp,
|
| H A D | AArch64InstrInfo.cpp | 2520 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2521 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2524 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
2547 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
2579 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2583 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
2588 if (!BaseOp->isReg() && !BaseOp->isFI()) in getMemOperandWithOffsetWidth()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 107 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset() argument
127 BaseOp = &MI.getOperand(1); in getBaseOffset()
139 BaseOp = &MI.getOperand(1); in getBaseOffset()
144 BaseOp = &MI.getOperand(2); in getBaseOffset()
158 BaseOp = &MI.getOperand(1); in getBaseOffset()
|
| H A D | ARMLoadStoreOptimizer.cpp | 1622 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1657 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1768 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1793 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1794 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
2731 MI->getOperand(BaseOp).setReg(NewBaseReg); in AdjustBaseAndOffset()
2863 int BaseOp = getBaseOperandIndex(Use); in DistributeIncrements() local
2864 if (BaseOp == -1) in DistributeIncrements()
2867 if (!Use.getOperand(BaseOp).isReg() || in DistributeIncrements()
2990 int BaseOp = getBaseOperandIndex(MI); in DistributeIncrements() local
[all …]
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
792 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
814 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
818 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
|
| H A D | LanaiInstrInfo.h | 77 const MachineOperand *&BaseOp,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 363 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1) in processAddUses() local
366 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
418 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1) in updateAddUses() local
422 BaseOp.setReg(newReg); in updateAddUses()
423 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
424 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
|
| H A D | HexagonInstrInfo.cpp | 1087 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1093 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1102 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1115 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1131 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1148 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1153 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
2979 if (!BaseOp || !BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
2981 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
[all …]
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 96 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
139 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | EvergreenInstructions.td | 675 field string BaseOp;
684 let BaseOp = name;
690 let BaseOp = name;
706 field string BaseOp;
714 let BaseOp = name;
720 let BaseOp = name;
|
| H A D | SIInstrInfo.cpp | 261 if (!BaseOp) { in getMemOperandsWithOffsetWidth()
266 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
302 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
324 if (BaseOp && !BaseOp->isFI()) in getMemOperandsWithOffsetWidth()
325 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
365 if (!BaseOp) // e.g. S_MEMTIME in getMemOperandsWithOffsetWidth()
367 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
379 if (BaseOp) in getMemOperandsWithOffsetWidth()
380 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
382 if (BaseOp) in getMemOperandsWithOffsetWidth()
[all …]
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1072 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
1080 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
1224 const MachineOperand *BaseOp; in describeLoadedValue() local
1225 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1249 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
|
| H A D | MachineSink.cpp | 1007 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
1010 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1013 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1026 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
|
| H A D | ModuloSchedule.cpp | 913 const MachineOperand *BaseOp; in computeDelta() local
916 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
923 if (!BaseOp->isReg()) in computeDelta()
926 Register BaseReg = BaseOp->getReg(); in computeDelta()
|
| H A D | MachinePipeliner.cpp | 2127 const MachineOperand *BaseOp; in computeDelta() local
2130 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2137 if (!BaseOp->isReg()) in computeDelta()
2140 Register BaseReg = BaseOp->getReg(); in computeDelta()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 96 const MachineOperand *&BaseOp,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1375 unsigned BaseOp = 0; in LowerXALUO() local
1382 BaseOp = M68kISD::ADD; in LowerXALUO()
1386 BaseOp = M68kISD::ADD; in LowerXALUO()
1390 BaseOp = M68kISD::SUB; in LowerXALUO()
1394 BaseOp = M68kISD::SUB; in LowerXALUO()
1401 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in LowerXALUO()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 533 const MachineOperand *&BaseOp,
|
| H A D | PPCInstrInfo.cpp | 2740 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2742 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
2744 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | Target.td | 1648 // let RowFields = BaseOp
1649 // All add instruction predicated/non-predicated will have to set their BaseOp
1652 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1653 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1654 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1320 const MachineOperand *&BaseOp, int64_t &Offset,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3669 unsigned BaseOp = 0; in lowerXALUO() local
3676 BaseOp = SystemZISD::SADDO; in lowerXALUO()
3681 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
3686 BaseOp = SystemZISD::UADDO; in lowerXALUO()
3691 BaseOp = SystemZISD::USUBO; in lowerXALUO()
3698 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
3734 unsigned BaseOp = 0; in lowerADDSUBCARRY() local
3744 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
3752 BaseOp = SystemZISD::SUBCARRY; in lowerADDSUBCARRY()
3764 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry); in lowerADDSUBCARRY()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6507 unsigned BaseOp; in lowerAddSubSatToMinMax() local
6514 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
6519 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
6524 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
6529 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
6563 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); in lowerAddSubSatToMinMax()
6569 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); in lowerAddSubSatToMinMax()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3678 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
3679 if (!BaseOp.isReg()) // Can be an MO_FrameIndex in getAddrModeFromMemoryOp()
3688 AM.BaseReg = BaseOp.getReg(); in getAddrModeFromMemoryOp()
3746 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
3748 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
3766 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3775 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
|