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Searched refs:CAYMAN_RING_TYPE_CP1_INDEX (Results 1 – 9 of 9) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ring.c71 case CAYMAN_RING_TYPE_CP1_INDEX: in radeon_ring_supports_scratch_reg()
527 static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
H A Dradeon_ni.c1491 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_rptr()
1507 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_wptr()
1521 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { in cayman_gfx_set_wptr()
1635 CAYMAN_RING_TYPE_CP1_INDEX, in cayman_cp_resume()
1736 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1742 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
2222 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cayman_startup()
H A Dradeon_si.c3481 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_enable()
3646 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_fini()
3706 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_resume()
3755 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; in si_cp_resume()
3760 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3764 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in si_cp_resume()
3766 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
4771 case CAYMAN_RING_TYPE_CP1_INDEX: in si_ib_parse()
6403 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in si_irq_process()
6728 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_startup()
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H A Dradeon_asic.c1705 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1825 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1965 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
2137 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2252 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
H A Dradeon_cik.c3528 case CAYMAN_RING_TYPE_CP1_INDEX: in cik_hdp_flush_cp_ring_emit()
4254 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in cik_cp_compute_enable()
4259 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cik_cp_compute_enable()
4367 idx = CAYMAN_RING_TYPE_CP1_INDEX; in cik_cp_compute_fini()
4586 idx = CAYMAN_RING_TYPE_CP1_INDEX; in cik_cp_compute_resume()
7093 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in cik_irq_set()
7094 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_irq_set()
8011 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cik_irq_process()
8427 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cik_startup()
8486 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_startup()
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H A Dradeon_fence.c1109 case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1"; in radeon_fence_get_timeline_name()
H A Dradeon_cs.c238 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; in radeon_cs_get_ring()
H A Dradeon_evergreen.c4534 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in evergreen_irq_set()
4885 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in evergreen_irq_process()
H A Dradeon.h145 #define CAYMAN_RING_TYPE_CP1_INDEX 1 macro