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Searched refs:CGTS_CU5_SP0_CTRL_REG__SP01_MASK (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h9823 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 macro
H A Dgfx_8_1_sh_mask.h11945 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 macro
H A Dgfx_8_0_sh_mask.h11547 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h24452 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro
H A Dgc_9_1_sh_mask.h25743 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro
H A Dgc_9_2_1_sh_mask.h25874 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro