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Searched refs:CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK (Results 1 – 11 of 11) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h2451 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Damdgpu_gfx_v6_0.c3336 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()
3341 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()
H A Damdgpu_gfx_v7_0.c4818 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state()
4823 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2378 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro
H A Dgfx_7_2_sh_mask.h1181 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_1_sh_mask.h2033 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_0_sh_mask.h1509 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11007 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12488 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12292 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17948 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro