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Searched refs:CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK (Results 1 – 8 of 8) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2400 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L macro
H A Dgfx_7_2_sh_mask.h1209 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
H A Dgfx_8_1_sh_mask.h2067 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
H A Dgfx_8_0_sh_mask.h1543 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11042 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12523 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12327 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17985 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro