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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h2392 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa macro
H A Dgfx_8_0_sh_mask.h1870 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11191 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT … macro
H A Dgc_9_1_sh_mask.h12672 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12470 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18146 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT … macro