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Searched refs:CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h2385 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 macro
H A Dgfx_8_0_sh_mask.h1863 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11198 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_9_1_sh_mask.h12679 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_9_2_1_sh_mask.h12477 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_10_1_0_sh_mask.h18157 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro