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Searched refs:CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK (Results 1 – 9 of 9) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c2210 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2756 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L macro
H A Dgfx_7_2_sh_mask.h1093 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
H A Dgfx_8_1_sh_mask.h1933 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
H A Dgfx_8_0_sh_mask.h1409 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10945 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_9_1_sh_mask.h12426 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_9_2_1_sh_mask.h12230 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_10_1_0_sh_mask.h17875 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro