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Searched refs:CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT (Results 1 – 11 of 11) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v9_0.c2766 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_init_gfx_power_gating()
4620 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_update_3d_clock_gating()
4674 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_update_coarse_grain_clock_gating()
H A Damdgpu_gfx_v10_0.c4127 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v10_0_update_3d_clock_gating()
4172 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v10_0_update_coarse_grain_clock_gating()
H A Damdgpu_gfx_v7_0.c3919 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v7_0_init_gfx_cgpg()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2849 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 macro
H A Dgfx_7_2_sh_mask.h3084 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h4220 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h3698 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1220 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_9_1_sh_mask.h1119 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1086 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6704 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro