1 /* $NetBSD: imxssireg.h,v 1.1 2010/11/13 07:11:03 bsh Exp $ */ 2 /* 3 * Copyright (c) 2009 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _ARM_IMX_IMXSSIREG_H 29 #define _ARM_IMX_IMXSSIREG_H 30 31 #define SSI_STX0 0x0000 32 #define SSI_STX1 0x0004 33 #define SSI_SRX0 0x0008 34 #define SSI_SRX1 0x000C 35 #define SSI_SCR 0x0010 36 #define SCR_CLK_IST __BIT(9) 37 #define SCR_TCH_EN __BIT(8) 38 #define SCR_SYS_CLK_EN __BIT(7) 39 #define SCR_I2SMODE_MASK ((0x3)<<5) 40 #define SCR_I2SMODE(n) ((n)<<5) 41 #define I2SMODE_NORMAL (0) 42 #define I2SMODE_MASTER (1) 43 #define I2SMODE_SLAVE (2) 44 #define SCR_SYN __BIT(4) 45 #define SCR_NET __BIT(3) 46 #define SCR_RE __BIT(2) 47 #define SCR_TE __BIT(1) 48 #define SCR_SSIEN __BIT(0) 49 #define SSI_SISR 0x0014 50 #define SSI_SIER 0x0018 51 #define SI_RDMAE __BIT(22) 52 #define SI_RIE __BIT(21) 53 #define SI_TDMAE __BIT(20) 54 #define SI_TIE __BIT(19) 55 #define SI_CMDAU_EN __BIT(18) 56 #define SI_CMDDU_EN __BIT(17) 57 #define SI_RXT_EN __BIT(16) 58 #define SI_RDR1_EN __BIT(15) 59 #define SI_RDR0_EN __BIT(14) 60 #define SI_TDE1_EN __BIT(13) 61 #define SI_TDE0_EN __BIT(12) 62 #define SI_ROE1_EN __BIT(11) 63 #define SI_ROE0_EN __BIT(10) 64 #define SI_TUE1_EN __BIT(9) 65 #define SI_TUE0_EN __BIT(8) 66 #define SI_RFS_EN __BIT(7) 67 #define SI_TFS_EN __BIT(6) 68 #define SI_RLS_EN __BIT(5) 69 #define SI_TLS_EN __BIT(4) 70 #define SI_RFF1_EN __BIT(3) 71 #define SI_RFF0_EN __BIT(2) 72 #define SI_TFE1_EN __BIT(1) 73 #define SI_TFE0_EN __BIT(0) 74 #define SSI_STCR 0x001C 75 #define SSI_SRCR 0x0020 76 #define CR_XEX __BIT(10) 77 #define CR_XBIT __BIT(9) 78 #define CR_FEN1 __BIT(8) 79 #define CR_FEN0 __BIT(7) 80 #define CR_FDIR __BIT(6) 81 #define CR_XDIR __BIT(5) 82 #define CR_SHFD __BIT(4) 83 #define CR_SHFD_MSB (0<<4) 84 #define CR_SHFD_LSB CR_SHFD 85 #define CR_SCKP __BIT(3) 86 #define CR_FSI __BIT(2) 87 #define CR_FSL __BIT(1) 88 #define CR_EFS __BIT(0) 89 #define SSI_STCCR 0x0024 90 #define SSI_SRCCR 0x0028 91 #define WL_SHIFT 13 92 #define WL_MASK (0xf << 13) 93 #define DC_SHIFT 8 94 #define DC_MASK (0xf << 8) 95 #define SSI_SFCSR 0x002C 96 #define SFCSR_RFCNT1_MASK (0xf << 28) 97 #define SFCSR_TFCNT1_MASK (0xf << 24) 98 #define SFCSR_RFWM1_MASK (0xf << 20) 99 #define SFCSR_TFWM1_MASK (0xf << 16) 100 #define SFCSR_RFCNT0_MASK (0xf << 12) 101 #define SFCSR_TFCNT0_MASK (0xf << 8) 102 #define SFCSR_RFWM0_MASK (0xf << 4) 103 #define SFCSR_TFWM0_MASK (0xf << 0) 104 #define SFCSR_RFWM1(x) (((x) & 0xf) << 20) 105 #define SFCSR_TFWM1(x) (((x) & 0xf) << 16) 106 #define SFCSR_RFWM0(x) (((x) & 0xf) << 4) 107 #define SFCSR_TFWM0(x) (((x) & 0xf) << 0) 108 #define SSI_SACNT 0x0038 109 #define SSI_SACSDD 0x003C 110 #define SSI_SACDAT 0x0040 111 #define SSI_SATAG 0x0044 112 #define SSI_STMSK 0x0048 113 #define SSI_SRMSK 0x004C 114 115 116 #define SSI_SIZE 0x100 117 118 119 #endif /* _ARM_IMX_IMXSSIREG_H */ 120