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Searched refs:DC_HPD5_INT_CONTROL (Results 1 – 7 of 7) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_r600.c907 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
912 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
3677 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3678 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3825 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3921 WREG32(DC_HPD5_INT_CONTROL, hpd5); in r600_irq_set()
4025 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
4027 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
H A Dradeon_cik.c6945 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6946 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7073 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7295 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7412 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7414 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7442 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7444 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
H A Dsid.h886 #define DC_HPD5_INT_CONTROL 0x6050 macro
H A Dcikd.h960 #define DC_HPD5_INT_CONTROL 0x6050 macro
H A Devergreend.h1352 #define DC_HPD5_INT_CONTROL 0x6050 macro
H A Dr600d.h863 #define DC_HPD5_INT_CONTROL 0x7dc4 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h890 #define DC_HPD5_INT_CONTROL 0x1814 macro