Searched refs:DMACSR_RESET (Results 1 – 6 of 6) sorted by relevance
79 dma->dd_csr = DMACSR_RESET; in scsi_init()372 dma->dd_csr = DMACSR_READ | DMACSR_RESET; in dma_start()378 dma->dd_csr = DMACSR_INITBUF | DMACSR_READ | DMACSR_RESET; in dma_start()429 dma->dd_csr = DMACSR_CLRCOMPLETE | DMACSR_RESET; in dma_done()
224 DMACSR_RESET | DMACSR_WRITE; in en_put()249 txdma->dd_csr = DMACSR_RESET | DMACSR_CLRCOMPLETE; in en_put()303 DMACSR_READ | DMACSR_RESET; in en_get()343 rxdma->dd_csr = DMACSR_RESET | DMACSR_CLRCOMPLETE; in en_get()
86 #define DMACSR_RESET 0x00100000 /* clr cmplt, sup, enable */ macro
100 #define DMACSR_RESET 0x00100000 /* clr cmplt, sup, enable */ macro
286 nd_bsw4(DD_CSR, DMACSR_RESET | DMACSR_CLRCOMPLETE); in nextdma_init()332 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); in nextdma_reset()755 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); in nextdma_enet_intr()878 DMACSR_INITBUFTURBO : DMACSR_INITBUF) | DMACSR_RESET | dmadir); in nextdma_start()
1556 DMACSR_INITBUF | DMACSR_RESET | in esp_dma_int()1609 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); in esp_dma_int()1616 DMACSR_INITBUF | DMACSR_RESET | in esp_dma_int()1696 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); in esp_dma_int()