| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 73 const DebugLoc &DL, unsigned DReg,
87 const DebugLoc &DL, unsigned DReg,
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
147 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR()
433 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
440 .addReg(DReg, 0, Lane); in createExtractSubreg()
478 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
484 .addReg(DReg) in createInsertSubreg()
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| H A D | ARMBaseInstrInfo.cpp | 4963 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4964 return DReg; in getCorrespondingDRegAndLane()
4970 return DReg; in getCorrespondingDRegAndLane()
4993 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse()
4999 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
5017 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
5068 .addReg(DReg, RegState::Undef) in setExecutionDomain()
5097 MIB.addReg(DReg, RegState::Define) in setExecutionDomain()
5098 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI))) in setExecutionDomain()
5273 if (!DReg || !MI.definesRegister(DReg, TRI)) in getPartialRegUpdateClearance()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 79 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
81 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| H A D | M68kDisassembler.cpp | 331 case M68kBeads::DReg: in buildBeadTable()
336 if (Op != M68kBeads::Reg && Op != M68kBeads::DReg) in buildBeadTable()
421 bool DA = (Op != M68kBeads::DReg) && Reader.readBits(1); in decodeReg()
527 case M68kBeads::DReg: in getInstruction()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 907 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
908 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg in adjustLiveRegs()
910 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs()
911 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
913 Defs &= ~(1 << DReg); in adjustLiveRegs()
939 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
940 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); in adjustLiveRegs()
942 pushReg(DReg); in adjustLiveRegs()
943 Defs &= ~(1 << DReg); in adjustLiveRegs()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 124 case M68kBeads::DReg: in encodeReg()
355 case M68kBeads::DReg: in encodeInstruction()
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| H A D | M68kBaseInfo.h | 61 DReg = 0x8, enumerator
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4860 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4863 unsigned TmpReg = DReg; in expandRotation()
4869 if (DReg == SReg) { in expandRotation()
4910 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4923 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
4973 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotationImm()
4985 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotation() local
4988 unsigned TmpReg = DReg; in expandDRotation()
5035 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotation()
5048 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotationImm() local
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 418 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
423 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8154 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint() local
8155 return std::make_pair(DReg, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
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