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Searched refs:DYN_GFX_CLK_OFF_EN (Results 1 – 15 of 15) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv730d.h91 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Dtrinityd.h181 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Dradeon_rv770_dpm.c138 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
140 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
177 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) in rv770_restore_cgcg()
181 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_restore_cgcg()
1637 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1668 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
H A Dsumod.h160 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Dradeon_cypress_dpm.c109 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
149 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
H A Dradeon_r600_dpm.c252 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
254 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
H A Dradeon_trinity_dpm.c451 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
H A Dradeon_sumo_dpm.c96 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
98 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
H A Drv770d.h166 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Dnid.h607 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Dsid.h259 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Devergreend.h145 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
H A Dr600d.h1320 # define DYN_GFX_CLK_OFF_EN (1 << 10) macro
H A Dradeon_ni_dpm.c1211 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h261 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro