| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 58 class DstOp {
67 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
68 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
520 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, in buildUAddo()
526 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, in buildUSubo()
532 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, in buildSAddo()
538 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, in buildSSubo()
557 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, in buildUAdde()
565 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, in buildUSube()
573 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, in buildSAdde()
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| H A D | CSEMIRBuilder.h | 56 void profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const;
58 void profileDstOps(ArrayRef<DstOp> Ops, GISelInstProfileBuilder &B) const { in profileDstOps()
59 for (const DstOp &Op : Ops) in profileDstOps()
72 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
82 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
88 bool checkCopyToDefsPossible(ArrayRef<DstOp> DstOps);
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
100 MachineInstrBuilder buildConstant(const DstOp &Res,
105 MachineInstrBuilder buildFConstant(const DstOp &Res,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.cpp | 65 void CSEMIRBuilder::profileDstOp(const DstOp &Op, in profileDstOp()
68 case DstOp::DstType::Ty_RC: in profileDstOp()
71 case DstOp::DstType::Ty_Reg: { in profileDstOp()
133 return llvm::all_of(DstOps, [](const DstOp &Op) { in checkCopyToDefsPossible()
134 DstOp::DstType DT = Op.getDstOpKind(); in checkCopyToDefsPossible()
135 return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC; in checkCopyToDefsPossible()
140 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps, in generateCopiesIfRequired()
145 const DstOp &Op = DstOps[0]; in generateCopiesIfRequired()
146 if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg) in generateCopiesIfRequired()
198 const DstOp &Dst = DstOps[0]; in buildInstr()
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| H A D | MachineIRBuilder.cpp | 343 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr, in buildLoad()
372 const DstOp &Dst, const SrcOp &BasePtr, in buildLoadFromOffset()
599 MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge()
610 SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); in buildUnmerge()
629 SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); in buildUnmerge()
650 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res, in buildBuildVectorTrunc()
731 for (DstOp Result : Results) in buildIntrinsic()
838 unsigned Opcode, const DstOp &OldValRes, in buildAtomicRMW()
931 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, in buildAtomicRMWFAdd()
1114 [&, this](const DstOp &Op) { in buildInstr()
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| H A D | LegalizerHelper.cpp | 6714 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, in SwapN()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRDFOpt.cpp | 121 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
138 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Linker/ |
| H A D | IRMover.cpp | 1256 MDNode *DstOp; in linkModuleFlagsMetadata() local
1258 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1272 if (!DstOp) { in linkModuleFlagsMetadata()
1280 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1292 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1318 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1328 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1342 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1365 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1379 MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 88 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
90 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
91 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.h | 70 uint16_t DstOp; member
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| H A D | X86MCInstLower.cpp | 1803 const MachineOperand &DstOp = MI->getOperand(0); in getShuffleComment() local
1807 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
2167 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2168 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
2246 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2247 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
2355 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2356 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
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| H A D | X86InstrInfo.cpp | 5572 unsigned Opcode = I->DstOp; in foldMemoryOperandImpl()
6259 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
6407 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
6544 return I->DstOp; in getOpcodeAfterMemoryUnfold()
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| H A D | X86InstrFoldTables.cpp | 5681 Table.push_back({Entry.DstOp, Entry.KeyOp, in addTableEntry()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MIRYamlMapping.h | 493 unsigned DstOp;
496 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
497 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
506 YamlIO.mapRequired("dstop", Sub.DstOp);
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1460 const MachineOperand &DstOp = MI->getOperand(0); in verifyPreISelGenericInstruction() local
1464 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) { in verifyPreISelGenericInstruction()
1679 const MachineOperand &DstOp = MI->getOperand(0); in visitMachineInstrBefore() local
1682 const Register DstReg = DstOp.getReg(); in visitMachineInstrBefore()
1724 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
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| H A D | MachineScheduler.cpp | 1830 const MachineOperand &DstOp = Copy->getOperand(0); in constrainLocalCopy() local
1831 Register DstReg = DstOp.getReg(); in constrainLocalCopy()
1832 if (!Register::isVirtualRegister(DstReg) || DstOp.isDead()) in constrainLocalCopy()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 273 MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size, in buildLoad()
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| /netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 4688 Record *DstOp = Dst->getOperator(); in createInstructionRenderer() local
4689 if (!DstOp->isSubClassOf("Instruction")) { in createInstructionRenderer()
4690 if (DstOp->isSubClassOf("ValueType")) in createInstructionRenderer()
4695 CodeGenInstruction *DstI = &Target.getInstruction(DstOp); in createInstructionRenderer()
5184 Record *DstOp = Dst->getOperator(); in runOnPattern() local
5185 if (!DstOp->isSubClassOf("Instruction")) in runOnPattern()
5188 auto &DstI = Target.getInstruction(DstOp); in runOnPattern()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 114 MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) { in buildLoad()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 422 std::make_pair(Sub.DstInst, Sub.DstOp)); in setupDebugValueTracking()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 207 std::initializer_list<llvm::DstOp> DstOps,
4100 unsigned Opcode, std::initializer_list<llvm::DstOp> DstOps, in emitInstr()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 7704 bit WithStride, DAGOperand DstOp>
7706 [!con((ins DstOp:$dst),
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