/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 154 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local 158 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses() 172 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy() 237 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local 240 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence() 251 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence() 262 bool IsAGPR = TRI->hasAGPRs(DstRC); in foldVGPRCopyIntoRegSequence() 589 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local 610 if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) { in runOnMachineFunction() 645 } else if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) { in runOnMachineFunction() [all …]
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H A D | AMDGPUInstructionSelector.cpp | 104 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local 108 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin() 479 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT() 518 if (!DstRC) in selectG_MERGE_VALUES() 579 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI)) in selectG_UNMERGE_VALUES() 727 if (!DstRC) in selectG_INSERT() 1135 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectRelocConstant() 1858 const TargetRegisterClass *DstRC in selectG_TRUNC() local 1860 if (!SrcRC || !DstRC) in selectG_TRUNC() 2168 if (!DstRC) in selectG_CONSTANT() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 252 if (SrcRC != DstRC) { in selectCopy() 278 const TargetRegisterClass *DstRC = in selectCopy() local 288 if (DstRC != SrcRC) { in selectCopy() 686 return (DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass || in canTurnIntoCOPY() 687 DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) && in canTurnIntoCOPY() 731 if (!DstRC || !SrcRC) in selectTruncOrPtrToInt() 737 if (canTurnIntoCOPY(DstRC, SrcRC)) in selectTruncOrPtrToInt() 744 if (DstRC == SrcRC) { in selectTruncOrPtrToInt() 751 } else if (DstRC == &X86::GR8RegClass) { in selectTruncOrPtrToInt() 863 if (canTurnIntoCOPY(SrcRC, DstRC)) in selectAnyext() [all …]
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H A D | X86InstrMMX.td | 126 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, 127 [(set DstRC:$dst, (Int SrcRC:$src))], d>, 129 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, 130 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>, 135 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, 137 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), 138 (ins DstRC:$src1, SrcRC:$src2), asm, 139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>, 141 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), 142 (ins DstRC:$src1, x86memop:$src2), asm, [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 151 const TargetRegisterClass *DstRC, in isCrossCopy() argument 156 if (DstRC == SrcRC) in isCrossCopy() 181 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy() 184 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy() 186 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy() 187 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy() 435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local 436 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes() 484 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local 485 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
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H A D | PeepholeOptimizer.cpp | 477 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local 478 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY() 479 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY() 585 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
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H A D | RegisterCoalescer.cpp | 479 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local 487 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters() 494 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters() 498 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters() 501 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters() 516 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters() 1351 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local 1353 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef() 1882 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local 1887 std::swap(SrcRC, DstRC); in joinCopy() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 176 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local 177 if (DstRC) in runOnMachineFunction() 178 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction() 226 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local 227 if (SrcRC == DstRC) { in runOnMachineFunction()
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/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 204 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local 282 if (DstRC) { in initialize() 283 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize() 286 DstRC = RC; in initialize() 485 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local 493 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns() 494 if (!DstRC) in collectPatterns() 533 DstRC)) in collectPatterns() 583 DstRC, in collectPatterns()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local 127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
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H A D | PPCVSXSwapRemoval.cpp | 922 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local 923 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables() 936 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MicroMips32r6InstrInfo.td | 660 dag OutOperandList = (outs DstRC:$rs); 672 dag OutOperandList = (outs DstRC:$fs); 682 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt); 683 dag OutOperandList = (outs DstRC:$fs); 696 dag OutOperandList = (outs DstRC:$impl); 718 dag OutOperandList = (outs DstRC:$rt); 730 dag OutOperandList = (outs DstRC:$rt); 740 dag OutOperandList = (outs DstRC:$rt); 885 dag OutOperandList = (outs DstRC:$ft); 921 dag OutOperandList = (outs DstRC:$ft); [all …]
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H A D | MipsInstrFPU.td | 128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft), 162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 171 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 176 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 865 const TargetRegisterClass *DstRC; in selectCopy() local 868 if (!DstRC) { in selectCopy() 916 getSubRegForClass(DstRC, TRI, SubReg); in selectCopy() 2829 const TargetRegisterClass *DstRC = in select() local 2831 if (!DstRC) in select() 2845 if (DstRC == SrcRC) { in select() 3151 const TargetRegisterClass *DstRC = in select() local 3695 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() local 3762 const TargetRegisterClass *DstRC = in emitExtractVectorElt() local 3764 if (!DstRC) { in emitExtractVectorElt() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.cpp | 282 const TargetRegisterClass *DstRC, in shouldCoalesce() argument 290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
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H A D | AVRRegisterInfo.h | 57 const TargetRegisterClass *DstRC,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.h | 60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
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H A D | HexagonRegisterInfo.cpp | 349 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument 360 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 159 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local 164 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg() 170 DstRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 179 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg() 614 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local 616 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.h | 160 const TargetRegisterClass *DstRC,
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H A D | SystemZRegisterInfo.cpp | 379 const TargetRegisterClass *DstRC, in shouldCoalesce() argument 387 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.h | 134 unsigned SubReg, const TargetRegisterClass *DstRC,
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H A D | AArch64RegisterInfo.cpp | 783 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument 786 ((DstRC->getID() == AArch64::GPR64RegClassID) || in shouldCoalesce() 787 (DstRC->getID() == AArch64::GPR64commonRegClassID)) && in shouldCoalesce()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 208 const TargetRegisterClass *DstRC,
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H A D | ARMBaseRegisterInfo.cpp | 857 const TargetRegisterClass *DstRC, in shouldCoalesce() argument 869 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce() 878 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); in shouldCoalesce()
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