| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfxhub_v1_0.c | 131 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
316 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
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| H A D | amdgpu_gfxhub_v2_0.c | 126 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
301 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
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| H A D | amdgpu_mmhub_v2_0.c | 113 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
292 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
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| H A D | amdgpu_mmhub_v1_0.c | 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
350 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
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| H A D | amdgpu_gmc_v7_0.c | 640 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
761 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
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| H A D | amdgpu_mmhub_v9_4.c | 195 ENABLE_L1_TLB, 1); in mmhub_v9_4_init_tlb_regs()
419 ENABLE_L1_TLB, 0); in mmhub_v9_4_gart_disable()
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| H A D | amdgpu_gmc_v8_0.c | 861 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
999 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
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| H A D | sid.h | 479 #define ENABLE_L1_TLB (1 << 0) macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hubp.h | 404 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
602 type ENABLE_L1_TLB;\
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| H A D | amdgpu_dcn10_hubp.c | 811 ENABLE_L1_TLB, 1, in hubp1_set_vm_context0_settings()
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| /netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_rv770.c | 921 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
998 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
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| H A D | rv770d.h | 467 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | nid.h | 181 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | sid.h | 477 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | cikd.h | 602 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | evergreend.h | 957 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | r600d.h | 334 #define ENABLE_L1_TLB (1 << 0) macro
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| H A D | radeon_ni.c | 1295 ENABLE_L1_TLB | in cayman_pcie_gart_enable()
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| H A D | radeon_r600.c | 1182 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1274 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()
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| H A D | radeon_evergreen.c | 2423 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2506 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_agp_enable()
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| H A D | radeon_si.c | 4306 ENABLE_L1_TLB | in si_pcie_gart_enable()
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| H A D | radeon_cik.c | 5460 ENABLE_L1_TLB | in cik_pcie_gart_enable()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | dce_hwseq.h | 710 type ENABLE_L1_TLB;\
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| H A D | amdgpu_dcn21_hubp.c | 351 ENABLE_L1_TLB, 1, in hubp21_set_vm_system_aperture_settings()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_hubp.c | 80 ENABLE_L1_TLB, 1, in hubp2_set_vm_system_aperture_settings()
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