Home
last modified time | relevance | path

Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 42) sorted by relevance

12

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp181 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
182 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
183 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
184 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
251 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
452 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
1654 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1663 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1739 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
[all …]
H A DSIISelLowering.cpp255 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
578 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
822 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SITargetLowering()
4508 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
4787 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
9609 case ISD::EXTRACT_VECTOR_ELT: in isCanonicalized()
10612 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
10613 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
10630 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
10631 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
[all …]
H A DAMDGPUISelLowering.cpp1462 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1463 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1473 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1481 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1513 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
2165 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2350 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ_CTTZ()
2351 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ_CTTZ()
2491 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2493 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
[all …]
H A DAMDGPUISelDAGToDAG.cpp320 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in isExtractHiElt()
348 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in stripExtractLoElt()
931 if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
932 BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
330 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_FP_ROUND()
388 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
413 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, in ScalarizeVecRes_VecInregOp()
450 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
568 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
570 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
625 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
3994 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, in WidenVecRes_EXTRACT_SUBVECTOR()
4777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, in WidenVecOp_BITCAST()
[all …]
H A DLegalizeTypesGeneric.cpp125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, in ExpandRes_BITCAST()
239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeFloatTypes.cpp65 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
247 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
1182 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
2221 case ISD::EXTRACT_VECTOR_ELT: in PromoteFloatResult()
2375 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT, in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2583 case ISD::EXTRACT_VECTOR_ELT: in SoftPromoteHalfResult()
2665 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftPromoteHalfRes_EXTRACT_VECTOR_ELT()
H A DLegalizeVectorOps.cpp1486 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in UnrollStrictFPOp()
1525 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1527 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
H A DLegalizeDAG.cpp1003 case ISD::EXTRACT_VECTOR_ELT: in LegalizeOp()
2972 case ISD::EXTRACT_VECTOR_ELT: in ExpandNode()
3058 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in ExpandNode()
3062 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, in ExpandNode()
3753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
3756 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
4378 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || in PromoteNode()
4793 case ISD::EXTRACT_VECTOR_ELT: { in PromoteNode()
4828 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
4877 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
H A DLegalizeIntegerTypes.cpp69 case ISD::EXTRACT_VECTOR_ELT: in PromoteIntegerResult()
577 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
1492 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; in PromoteIntegerOperand()
2067 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandIntegerResult()
4690 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntRes_EXTRACT_SUBVECTOR()
4824 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op, in PromoteIntRes_CONCAT_VECTORS()
4897 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
4948 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming, in PromoteIntOp_CONCAT_VECTORS()
H A DDAGCombiner.cpp654 case ISD::EXTRACT_VECTOR_ELT: in getStoreSource()
5704 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
12050 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
12069 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy, in visitTRUNCATE()
16787 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
18164 InsertVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineInsertEltToShuffle()
18299 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
18797 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, in visitEXTRACT_VECTOR_ELT()
19254 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
19509 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
[all …]
H A DSelectionDAG.cpp3404 case ISD::EXTRACT_VECTOR_ELT: { in computeKnownBits()
4067 case ISD::EXTRACT_VECTOR_ELT: { in ComputeNumSignBits()
4369 case ISD::EXTRACT_VECTOR_ELT: { in isKnownNeverNaN()
4465 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT || in FoldBUILD_VECTOR()
4981 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && in getNode()
5732 case ISD::EXTRACT_VECTOR_ELT: in getNode()
5756 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in getNode()
5811 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), in getNode()
9806 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchBinOpReduction()
9944 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, in UnrollVectorOp()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h505 EXTRACT_VECTOR_ELT, enumerator
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp185 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1243 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1643 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
1668 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1703 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1710 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1726 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp373 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
1883 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1931 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
1933 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2169 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2357 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2359 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2367 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2581 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
4857 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector, in ReplaceLoadVector()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
263 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
982 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in ARMTargetLowering()
8322 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
14113 if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformVMOVrhCombine()
14396 if (Ext.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in PerformExtractEltToVMOVRRD()
14413 return V->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformExtractEltToVMOVRRD()
14433 ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformExtractEltToVMOVRRD()
16279 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
646 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SystemZTargetLowering()
4952 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
5473 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
5821 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
5834 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
6161 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), EltVT, in combineEXTRACT_VECTOR_ELT()
6222 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
6230 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
6288 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_EXTEND()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2008 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in X86TargetLowering()
8259 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in LowerBuildVectorv4x32()
8457 case ISD::EXTRACT_VECTOR_ELT: in findEltLoadSrc()
9114 if (Opc != ISD::EXTRACT_VECTOR_ELT) { in buildFromShuffleMostly()
10265 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTORAsVariablePermute()
21787 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
21788 RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
22058 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchScalarReduction()
22225 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in MatchVectorAllZeroTest()
48066 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFMA()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/utils/
H A Dupdate_mir_test_checks.py259 EXTRACT_VECTOR_ELT='EVEC',
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp124 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
228 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
565 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in buildHvxVectorReg()
1276 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerHvxConcatVectors()
1278 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, in LowerHvxConcatVectors()
2105 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); in LowerHvxOperation()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp1053 if (ISD == ISD::EXTRACT_VECTOR_ELT && in getVectorInstrCost()
1101 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
H A DREADME_ALTIVEC.txt314 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp909 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in AArch64TargetLowering()
1377 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
1470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForFixedLengthSVE()
4556 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
8224 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in ReconstructShuffle()
9775 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
13185 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in tryCombineFixedPointConvert()
13417 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performUADDVCombine()
13440 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in performUADDVCombine()
16042 if (InsertElt.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in removeRedundantInsertVectorElt()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp423 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom); in RISCVTargetLowering()
444 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
495 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
562 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
641 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
751 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
1970 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, in LowerOperation()
2084 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
3212 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, Idx); in lowerEXTRACT_VECTOR_ELT()
3234 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, in lowerEXTRACT_VECTOR_ELT()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp298 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
313 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1719 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2741 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); in lowerEXTRACT_VECTOR_ELT()

12