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Searched refs:FMT_BIT_DEPTH_CONTROL (Results 1 – 13 of 13) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddce_opp.h47 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
92 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
93 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
94 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
95 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
100 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
109 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
110 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
111 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
112 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
[all …]
H A Damdgpu_dce_opp.c116 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
141 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
170 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
175 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
180 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
242 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
252 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
274 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
279 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
309 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_opp.c60 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in opp1_set_truncation()
71 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
128 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
H A Ddcn10_opp.h39 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
56 uint32_t FMT_BIT_DEPTH_CONTROL; \
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_dce_v10_0.c544 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
547 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
548 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt()
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
560 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
561 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v10_0_program_fmt()
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
[all …]
H A Damdgpu_dce_v11_0.c570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt()
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
586 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
587 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v11_0_program_fmt()
595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
596 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
599 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
[all …]
H A Dsid.h2106 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 macro
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dcikd.h989 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
H A Devergreend.h1378 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
H A Dr600d.h1247 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
H A Dradeon_r600.c353 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
H A Dradeon_evergreen.c1355 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
H A Dradeon_cik.c8867 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()