1 /* $NetBSD: epcomreg.h,v 1.4 2021/11/21 08:25:26 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 19 * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 20 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 25 * THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _EPCOMREG_H_ 29 #define _EPCOMREG_H_ 30 31 #define EPCOM_FREQ 7372800 32 #define EPCOMSPEED2BRD(b) ((EPCOM_FREQ / (16 * (b))) - 1) 33 34 35 /* UART Data Register */ 36 #define EPCOM_Data 0x00000000UL 37 38 /* UART Receive Status/Error Clear Register */ 39 #define EPCOM_RXSts 0x00000004UL 40 #define RXSts_FE 0x01 41 #define RXSts_PE 0x02 42 #define RXSts_BE 0x04 43 #define RXSts_OE 0x08 44 45 /* UART Line Control Register High */ 46 #define EPCOM_LinCtrlHigh 0x00000008UL 47 #define LinCtrlHigh_BRK 0x01 48 #define LinCtrlHigh_PEN 0x02 49 #define LinCtrlHigh_EPS 0x04 50 #define LinCtrlHigh_STP2 0x08 51 #define LinCtrlHigh_FEN 0x10 52 #define LinCtrlHigh_WLEN 0x60 53 54 /* UART Line Control Register Middle */ 55 #define EPCOM_LinCtrlMid 0x0000000cUL 56 57 /* UART Line Control Register Low */ 58 #define EPCOM_LinCtrlLow 0x00000010UL 59 60 /* UART control register */ 61 #define EPCOM_Ctrl 0x00000014UL 62 #define Ctrl_UARTE 0x01 /* UART Enable */ 63 #define Ctrl_MSIE 0x08 /* Modem Status Interrupt Enable */ 64 #define Ctrl_RIE 0x10 /* Receive Interrupt Enable */ 65 #define Ctrl_TIE 0x20 /* Transmit Interrupt Enable */ 66 #define Ctrl_RTIE 0x40 /* Receive Timeout Enable */ 67 #define Ctrl_LBE 0x80 /* Loopback Enable */ 68 69 /* UART Flag register */ 70 #define EPCOM_Flag 0x00000018UL 71 #define Flag_CTS 0x01 /* Clear To Send status */ 72 #define Flag_DSR 0x02 /* Data Set Ready status */ 73 #define Flag_DCD 0x04 /* Data Carrier Detect status */ 74 #define Flag_BUSY 0x08 /* UART Busy */ 75 #define Flag_RXFE 0x10 /* Receive FIFO Empty */ 76 #define Flag_TXFF 0x20 /* Transmit FIFO Full */ 77 #define Flag_RXFF 0x40 /* Receive FIFO Full */ 78 #define Flag_TXFE 0x80 /* Transmit FIFO Empty */ 79 80 /* UART Interrupt Identification and Interrupt Clear Register */ 81 #define EPCOM_IntIDIntClr 0x0000001cUL 82 #define IntIDIntClr_MIS 0x01 /* Modem Interrupt Status */ 83 #define IntIDIntClr_RIS 0x01 /* Receive Interrupt Status */ 84 #define IntIDIntClr_TIS 0x01 /* Transmit Interrupt Status */ 85 #define IntIDIntClr_RTIS 0x01 /* Receive Timeout Interrupt Status */ 86 87 /* UART Modem Control Register */ 88 #define EPCOM_ModemCtrl 0x00000100UL 89 #define ModemCtrl_DTR 0x01 /* DTR output signal */ 90 #define ModemCtrl_RTS 0x02 /* RTS output signal */ 91 92 /* UART Modem Status Register */ 93 #define EPCOM_ModemSts 0x00000104UL 94 #define ModemSts_DCTS 0x01 /* Delta CTS */ 95 #define ModemSts_DDSR 0x02 /* Delta DSR */ 96 #define ModemSts_TERI 0x04 /* Trailing Edge Ring Indicator */ 97 #define ModemSts_DDCD 0x08 /* Delta DCD */ 98 #define ModemSts_CTS 0x10 /* Inverse CTSn input pin */ 99 #define ModemSts_DSR 0x20 /* Inverse of the DSRn pin */ 100 #define ModemSts_RI 0x40 /* Inverse of RI input pin */ 101 #define ModemSts_DCD 0x80 /* Inverse of DCDn input pin */ 102 103 #endif /* _EPCOMREG_H_ */ 104