1 /* $NetBSD: esmreg.h,v 1.6 2005/12/11 12:22:49 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 Rene Hexel <rh@NetBSD.org> 5 * All rights reserved. 6 * 7 * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * Taku Id: maestro_reg.h,v 1.10 2000/08/29 17:27:29 taku Exp 32 * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro_reg.h,v 1.1 2000/09/06 20:10:54 cg Exp 33 */ 34 35 #ifndef ESM_REG_H_INCLUDED 36 #define ESM_REG_H_INCLUDED 37 38 /* ----------------------------- 39 * PCI config registers 40 */ 41 42 /* Legacy emulation */ 43 #define CONF_LEGACY 0x40 44 45 #define LEGACY_DISABLED 0x8000 46 47 /* Chip configurations */ 48 #define CONF_MAESTRO 0x50 49 #define MAESTRO_CHIBUS 0x00100000 50 #define MAESTRO_POSTEDWRITE 0x00000080 51 #define MAESTRO_DMA_PCITIMING 0x00000040 52 #define MAESTRO_SWAP_LR 0x00000010 53 54 /* ACPI configurations */ 55 #define CONF_ACPI_STOPCLOCK 0x54 56 #define ACPI_PART_2ndC_CLOCK 15 57 #define ACPI_PART_CODEC_CLOCK 14 58 #define ACPI_PART_978 13 /* Docking station or something */ 59 #define ACPI_PART_SPDIF 12 60 #define ACPI_PART_GLUE 11 /* What? */ 61 #define ACPI_PART_DAA 10 62 #define ACPI_PART_PCI_IF 9 63 #define ACPI_PART_HW_VOL 8 64 #define ACPI_PART_GPIO 7 65 #define ACPI_PART_ASSP 6 66 #define ACPI_PART_SB 5 67 #define ACPI_PART_FM 4 68 #define ACPI_PART_RINGBUS 3 69 #define ACPI_PART_MIDI 2 70 #define ACPI_PART_GAME_PORT 1 71 #define ACPI_PART_WP 0 72 73 /* ----------------------------- 74 * I/O ports 75 */ 76 77 /* Direct Sound Processor (aka WP) */ 78 #define PORT_DSP_DATA 0x00 /* WORD RW */ 79 #define PORT_DSP_INDEX 0x02 /* WORD RW */ 80 #define PORT_INT_STAT 0x04 /* WORD RW */ 81 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 82 83 /* WaveCache */ 84 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 85 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 86 #define WAVCACHE_PCMBAR 0x1fc 87 #define WAVCACHE_WTBAR 0x1f0 88 #define WAVCACHE_BASEADDR_SHIFT 12 89 90 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 91 #define WAVCACHE_CHCTL_U8 0x0004 92 #define WAVCACHE_CHCTL_STEREO 0x0002 93 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001 94 95 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 96 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200 97 #define WAVCACHE_ENABLED 0x0100 98 #define WAVCACHE_CH_60_ENABLED 0x0080 99 #define WAVCACHE_WTSIZE_MASK 0x0060 100 #define WAVCACHE_WTSIZE_1MB 0x0000 101 #define WAVCACHE_WTSIZE_2MB 0x0020 102 #define WAVCACHE_WTSIZE_4MB 0x0040 103 #define WAVCACHE_WTSIZE_8MB 0x0060 104 #define WAVCACHE_SGC_MASK 0x000c 105 #define WAVCACHE_SGC_DISABLED 0x0000 106 #define WAVCACHE_SGC_40_47 0x0004 107 #define WAVCACHE_SGC_32_47 0x0008 108 #define WAVCACHE_TESTMODE 0x0001 109 110 /* Host Interruption */ 111 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 112 #define HOSTINT_CTRL_SOFT_RESET 0x8000 113 #define HOSTINT_CTRL_DSOUND_RESET 0x4000 114 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 115 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 116 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 117 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 118 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 119 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 120 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 121 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 122 123 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 124 #define HOSTINT_STAT_HWVOL 0x40 125 #define HOSTINT_STAT_ASSP 0x10 126 #define HOSTINT_STAT_ISDN 0x08 127 #define HOSTINT_STAT_DSOUND 0x04 128 #define HOSTINT_STAT_MPU401 0x02 129 #define HOSTINT_STAT_SB 0x01 130 131 /* Hardware volume */ 132 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 133 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 134 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 135 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 136 137 /* CODEC */ 138 #define PORT_CODEC_CMD 0x30 /* BYTE W */ 139 #define CODEC_CMD_READ 0x80 140 #define CODEC_CMD_WRITE 0x00 141 #define CODEC_CMD_ADDR_MASK 0x7f 142 143 #define PORT_CODEC_STAT 0x30 /* BYTE R */ 144 #define CODEC_STAT_MASK 0x01 145 #define CODEC_STAT_RW_DONE 0x00 146 #define CODEC_STAT_PROGLESS 0x01 147 148 #define PORT_CODEC_REG 0x32 /* WORD RW */ 149 150 /* Ring bus control */ 151 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 152 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000 153 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 154 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 155 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000 156 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 157 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 158 159 #define RINGBUS_SRC_MIC 20 160 #define RINGBUS_SRC_I2S 16 161 #define RINGBUS_SRC_ADC 12 162 #define RINGBUS_SRC_MODEM 8 163 #define RINGBUS_SRC_DSOUND 4 164 #define RINGBUS_SRC_ASSP 0 165 166 #define RINGBUS_DEST_MONORAL 000 167 #define RINGBUS_DEST_STEREO 010 168 #define RINGBUS_DEST_NONE 0 169 #define RINGBUS_DEST_DAC 1 170 #define RINGBUS_DEST_MODEM_IN 2 171 #define RINGBUS_DEST_RESERVED3 3 172 #define RINGBUS_DEST_DSOUND_IN 4 173 #define RINGBUS_DEST_ASSP_IN 5 174 175 /* General Purpose I/O */ 176 #define PORT_GPIO_DATA 0x60 /* WORD RW */ 177 #define PORT_GPIO_MASK 0x64 /* WORD RW */ 178 #define PORT_GPIO_DIR 0x68 /* WORD RW */ 179 180 /* Application Specific Signal Processor */ 181 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 182 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 183 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 184 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 185 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 186 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 187 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 188 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 189 190 191 /* ----------------------------- 192 * Wave Processor Indexed Data Registers. 193 */ 194 195 #define WPREG_DATA_PORT 0 196 #define WPREG_CRAM_PTR 1 197 #define WPREG_CRAM_DATA 2 198 #define WPREG_WAVE_DATA 3 199 #define WPREG_WAVE_PTR_LOW 4 200 #define WPREG_WAVE_PTR_HIGH 5 201 202 #define WPREG_TIMER_FREQ 6 203 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 204 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5 205 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 206 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0 207 208 #define WPREG_WAVE_ROMRAM 7 209 #define WP_WAVE_VIRTUAL_ENABLED 0x0400 210 #define WP_WAVE_8BITRAM_ENABLED 0x0200 211 #define WP_WAVE_DRAM_ENABLED 0x0100 212 #define WP_WAVE_RAMSPLIT_MASK 0x00ff 213 #define WP_WAVE_RAMSPLIT_SHIFT 0 214 215 #define WPREG_BASE 12 216 #define WP_PARAOUT_BASE_MASK 0xf000 217 #define WP_PARAOUT_BASE_SHIFT 12 218 #define WP_PARAIN_BASE_MASK 0x0f00 219 #define WP_PARAIN_BASE_SHIFT 8 220 #define WP_SERIAL0_BASE_MASK 0x00f0 221 #define WP_SERIAL0_BASE_SHIFT 4 222 #define WP_SERIAL1_BASE_MASK 0x000f 223 #define WP_SERIAL1_BASE_SHIFT 0 224 225 #define WPREG_TIMER_ENABLE 17 226 #define WPREG_TIMER_START 23 227 228 229 /* ----------------------------- 230 * Audio Processing Unit. 231 */ 232 #define APUREG_APUTYPE 0 233 #define APU_DMA_ENABLED 0x4000 234 #define APU_INT_ON_LOOP 0x2000 235 #define APU_ENDCURVE 0x1000 236 #define APU_APUTYPE_MASK 0x00f0 237 #define APU_FILTERTYPE_MASK 0x000c 238 #define APU_FILTERQ_MASK 0x0003 239 240 /* APU types */ 241 #define APU_APUTYPE_SHIFT 4 242 243 #define APUTYPE_INACTIVE 0 244 #define APUTYPE_16BITLINEAR 1 245 #define APUTYPE_16BITSTEREO 2 246 #define APUTYPE_8BITLINEAR 3 247 #define APUTYPE_8BITSTEREO 4 248 #define APUTYPE_8BITDIFF 5 249 #define APUTYPE_DIGITALDELAY 6 250 #define APUTYPE_DUALTAP_READER 7 251 #define APUTYPE_CORRELATOR 8 252 #define APUTYPE_INPUTMIXER 9 253 #define APUTYPE_WAVETABLE 10 254 #define APUTYPE_RATECONV 11 255 #define APUTYPE_16BITPINGPONG 12 256 /* APU type 13 through 15 are reserved. */ 257 258 /* Filter types */ 259 #define APU_FILTERTYPE_SHIFT 2 260 261 #define FILTERTYPE_2POLE_LOPASS 0 262 #define FILTERTYPE_2POLE_BANDPASS 1 263 #define FILTERTYPE_2POLE_HIPASS 2 264 #define FILTERTYPE_1POLE_LOPASS 3 265 #define FILTERTYPE_1POLE_HIPASS 4 266 #define FILTERTYPE_PASSTHROUGH 5 267 268 /* Filter Q */ 269 #define APU_FILTERQ_SHIFT 0 270 271 #define FILTERQ_LESSQ 0 272 #define FILTERQ_MOREQ 3 273 274 /* APU register 2 */ 275 #define APUREG_FREQ_LOBYTE 2 276 #define APU_FREQ_LOBYTE_MASK 0xff00 277 #define APU_plus6dB 0x0010 278 279 /* APU register 3 */ 280 #define APUREG_FREQ_HIWORD 3 281 #define APU_FREQ_HIWORD_MASK 0x0fff 282 283 /* Frequency */ 284 #define APU_FREQ_LOBYTE_SHIFT 8 285 #define APU_FREQ_HIWORD_SHIFT 0 286 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 287 288 /* APU register 4 */ 289 #define APUREG_WAVESPACE 4 290 #define APU_STEREO 0x8000 291 #define APU_USE_SYSMEM 0x4000 292 #define APU_PCMBAR_MASK 0x6000 293 #define APU_64KPAGE_MASK 0xff00 294 295 /* PCM Base Address Register selection */ 296 #define APU_PCMBAR_SHIFT 13 297 298 /* 64KW (==128KB) Page */ 299 #define APU_64KPAGE_SHIFT 8 300 301 /* APU register 5 - 7 */ 302 #define APUREG_CURPTR 5 303 #define APUREG_ENDPTR 6 304 #define APUREG_LOOPLEN 7 305 306 /* APU register 8 */ 307 #define APUREG_EFFECTS_ENV 8 308 309 /* APU register 9 */ 310 #define APUREG_AMPLITUDE 9 311 #define APU_AMPLITUDE_NOW_MASK 0xff00 312 #define APU_AMPLITUDE_DEST_MASK 0x00ff 313 314 /* Amplitude now? */ 315 #define APU_AMPLITUDE_NOW_SHIFT 8 316 317 /* APU register 10 */ 318 #define APUREG_POSITION 10 319 #define APU_RADIUS_MASK 0x00c0 320 #define APU_PAN_MASK 0x003f 321 322 /* Radius control. */ 323 #define APU_RADIUS_SHIFT 6 324 #define RADIUS_CENTERCIRCLE 0 325 #define RADIUS_MIDDLE 1 326 #define RADIUS_OUTSIDE 2 327 328 /* Polar pan. */ 329 #define APU_PAN_SHIFT 0 330 #define PAN_RIGHT 0x00 331 #define PAN_FRONT 0x08 332 #define PAN_LEFT 0x10 333 334 /* APU register 11 */ 335 #define APUREG_ROUTE 11 336 #define ROUTE_PARALLEL 0x14 337 338 339 /* ----------------------------- 340 * Limits. 341 */ 342 #define WPWA_MAX ((1 << 22) - 1) 343 #define WPWA_MAXADDR ((1 << 23) - 1) 344 #define MAESTRO_MAXADDR ((1 << 28) - 1) 345 #define WPTIMER_MINDIV 4 346 #define WPTIMER_MAXDIV (32 << 8) 347 348 #endif /* ESM_REG_H_INCLUDED */ 349