/netbsd/external/apache2/llvm/dist/clang/lib/CodeGen/ |
H A D | CodeGenTypeCache.h | 39 llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy; member
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H A D | CGBuiltin.cpp | 6458 Ty = HalfTy; in EmitCommonNeonBuiltinExpr() 9769 llvm::Type *FTy = HalfTy; in EmitAArch64BuiltinExpr() 9794 llvm::Type* FTy = HalfTy; in EmitAArch64BuiltinExpr() 11008 Ty = HalfTy; in EmitAArch64BuiltinExpr() 11017 Ty = HalfTy; in EmitAArch64BuiltinExpr() 11098 Ty = HalfTy; in EmitAArch64BuiltinExpr() 11107 Ty = HalfTy; in EmitAArch64BuiltinExpr() 11116 Ty = HalfTy; in EmitAArch64BuiltinExpr() 11125 Ty = HalfTy; in EmitAArch64BuiltinExpr() 11134 Ty = HalfTy; in EmitAArch64BuiltinExpr() [all …]
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H A D | ItaniumCXXABI.cpp | 4167 getContext().UnsignedInt128Ty, getContext().HalfTy, in EmitFundamentalRTTIDescriptors()
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H A D | CodeGenModule.cpp | 115 HalfTy = llvm::Type::getHalfTy(LLVMContext); in CodeGenModule()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 4352 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant() 4362 LLT NVT = HalfTy; in narrowScalarShiftByConstant() 4363 unsigned NVTBits = HalfTy.getSizeInBits(); in narrowScalarShiftByConstant() 4462 const LLT HalfTy = LLT::scalar(NewBitSize); in narrowScalarShift() local 4491 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift() 4494 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); in narrowScalarShift() 4495 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); in narrowScalarShift() 4503 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); in narrowScalarShift() 4514 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); in narrowScalarShift() 4516 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); in narrowScalarShift() [all …]
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H A D | CombinerHelper.cpp | 2204 LLT HalfTy = LLT::scalar(HalfSize); in applyCombineShiftToUnmerge() local 2207 auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg); in applyCombineShiftToUnmerge() 2219 Narrowed = Builder.buildLShr(HalfTy, Narrowed, in applyCombineShiftToUnmerge() 2220 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge() 2223 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge() 2232 Narrowed = Builder.buildShl(HalfTy, Narrowed, in applyCombineShiftToUnmerge() 2236 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge() 2241 HalfTy, Unmerge.getReg(1), in applyCombineShiftToUnmerge() 2242 Builder.buildConstant(HalfTy, HalfSize - 1)); in applyCombineShiftToUnmerge() 2256 HalfTy, Unmerge.getReg(1), in applyCombineShiftToUnmerge() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.h | 127 LLT HalfTy,
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H A D | AMDGPURegisterBankInfo.cpp | 648 LLT HalfTy, in split64BitValueForMapping() argument 650 assert(HalfTy.getSizeInBits() == 32); in split64BitValueForMapping() 652 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() 2192 LLT HalfTy = getHalfSizedType(DstTy); in applyMappingImpl() local 2207 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingImpl() 2213 setRegsToType(MRI, Src2Regs, HalfTy); in applyMappingImpl() 2215 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl() 2271 LLT HalfTy = getHalfSizedType(DstTy); in applyMappingImpl() local 2294 setRegsToType(MRI, Src0Regs, HalfTy); in applyMappingImpl() 2299 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingImpl() [all …]
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/netbsd/external/apache2/llvm/dist/clang/include/clang/AST/ |
H A D | BuiltinTypes.def | 201 FLOATING_TYPE(Half, HalfTy) 213 FLOATING_TYPE(Float16, HalfTy)
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H A D | ASTContext.h | 1025 CanQualType HalfTy; // [OpenCL 6.1.1.1], ARM NEON variable
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/netbsd/external/apache2/llvm/dist/llvm/lib/IR/ |
H A D | LLVMContextImpl.cpp | 28 HalfTy(C, Type::HalfTyID), in LLVMContextImpl()
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H A D | Type.cpp | 182 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
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H A D | LLVMContextImpl.h | 1429 Type VoidTy, LabelTy, HalfTy, BFloatTy, FloatTy, DoubleTy, MetadataTy,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 336 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2); in typeSplit() local 337 return { HalfTy, HalfTy }; in typeSplit() 1318 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxConcatVectors() local 1319 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors() 1321 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors() 1795 MVT HalfTy = typeSplit(ResTy).first; in SplitHvxPairOp() local 1796 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL); in SplitHvxPairOp() 1797 SDValue H = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsH); in SplitHvxPairOp()
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H A D | HexagonISelDAGToDAGHVX.cpp | 992 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), in materialize() local 996 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize() 1148 MVT HalfTy = getSingleVT(MVT::i8); in packp() local 1151 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) }; in packp()
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H A D | HexagonISelLowering.cpp | 2490 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2); in buildVector64() local 2493 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG); in buildVector64() 2496 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG); in buildVector64()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.h | 324 LLT HalfTy, LLT ShiftAmtTy);
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/netbsd/external/apache2/llvm/dist/clang/lib/AST/ |
H A D | PrintfFormatString.cpp | 580 return Ctx.HalfTy; in getScalarArgType()
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H A D | ASTContext.cpp | 1478 InitBuiltinType(HalfTy, BuiltinType::Half); in InitBuiltinTypes() 3819 return SVE_ELTTY(HalfTy, 8, 1); in getBuiltinVectorTypeInfo() 3821 return SVE_ELTTY(HalfTy, 8, 2); in getBuiltinVectorTypeInfo() 3823 return SVE_ELTTY(HalfTy, 8, 3); in getBuiltinVectorTypeInfo() 3825 return SVE_ELTTY(HalfTy, 8, 4); in getBuiltinVectorTypeInfo() 3857 return {ElBits == 16 ? HalfTy : (ElBits == 32 ? FloatTy : DoubleTy), \ in getBuiltinVectorTypeInfo() 6265 case Float16Rank: return HalfTy; in getFloatingTypeOfSizeWithinDomain() 6267 case HalfRank: return HalfTy; in getFloatingTypeOfSizeWithinDomain() 10369 Type = Context.HalfTy; in DecodeTypeFromStr()
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/netbsd/external/apache2/llvm/dist/clang/lib/Sema/ |
H A D | SemaExpr.cpp | 3820 Ty = Context.HalfTy; in ActOnNumericConstant() 13878 assert((isVector(ResultTy, Context.HalfTy) || in convertHalfVecBinOp() 13881 assert(isVector(LHS.get()->getType(), Context.HalfTy) && in convertHalfVecBinOp() 13882 isVector(RHS.get()->getType(), Context.HalfTy) && in convertHalfVecBinOp() 13944 return VT->getElementType().getCanonicalType() == Ctx.HalfTy; in needsConversionOfHalfVec() 14166 (Opc == BO_Comma || isVector(RHS.get()->getType(), Context.HalfTy) == in CreateBuiltinBinOp() 14167 isVector(LHS.get()->getType(), Context.HalfTy)) && in CreateBuiltinBinOp() 14863 return convertVector(UO, Context.HalfTy, *this); in CreateBuiltinUnaryOp()
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H A D | OpenCLBuiltins.td | 306 def Half : Type<"half", QualType<"Context.HalfTy">>;
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H A D | SemaType.cpp | 1518 case DeclSpec::TST_half: Result = Context.HalfTy; break; in ConvertDeclSpecToType()
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H A D | SemaChecking.cpp | 2076 return Context.HalfTy; in getNeonEltType()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 11107 auto *HalfTy = HalfV->getType(); in areExtractShuffleVectors() local 11109 2 * HalfTy->getPrimitiveSizeInBits().getFixedSize(); in areExtractShuffleVectors()
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/netbsd/external/apache2/llvm/dist/clang/lib/Serialization/ |
H A D | ASTReader.cpp | 6876 T = Context.HalfTy; in GetType()
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