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Searched refs:Hi0 (Results 1 – 5 of 5) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4435 SDValue Lo0, Hi0; in splitBinaryVectorOp() local
4436 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0); in splitBinaryVectorOp()
4444 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp()
4457 SDValue Lo0, Hi0; in splitTernaryVectorOp() local
4458 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0); in splitTernaryVectorOp()
4468 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2, in splitTernaryVectorOp()
8213 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One); in LowerSELECT() local
8216 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); in LowerSELECT()
H A DAMDGPUISelDAGToDAG.cpp1027 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in SelectADD_SUB_I64() local
1055 SDValue(Hi0, 0), in SelectADD_SUB_I64()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2885 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; in SplitVecOp_VSETCC() local
2887 GetSplitVector(N->getOperand(0), Lo0, Hi0); in SplitVecOp_VSETCC()
2896 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
H A DTargetLowering.cpp4036 SDValue Lo0, Lo1, Hi0, Hi1; in SimplifySetCC() local
4037 if (IsConcat(N0.getOperand(0), Lo0, Hi0) && in SimplifySetCC()
4040 DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); in SimplifySetCC()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8785 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); in isExtendedBUILD_VECTOR() local
8788 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) in isExtendedBUILD_VECTOR()
8791 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && in isExtendedBUILD_VECTOR()
8795 if (Hi0->isNullValue() && Hi1->isNullValue()) in isExtendedBUILD_VECTOR()