Searched refs:I915_MAX_PIPES (Results 1 – 14 of 14) sorted by relevance
22 unsigned int data_rate[I915_MAX_PIPES];23 u8 num_active_planes[I915_MAX_PIPES];
498 int min_cdclk[I915_MAX_PIPES];500 u8 min_voltage_level[I915_MAX_PIPES];1306 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
307 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
107 enum pipe ret = I915_MAX_PIPES; in intel_dp_mst_master_trans_compute()134 if (ret == I915_MAX_PIPES) in intel_dp_mst_master_trans_compute()
452 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init()
113 I915_MAX_PIPES = _PIPE_EDP enumerator
15130 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()15336 u64 put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()18609 } cursor[I915_MAX_PIPES];18615 } pipe[I915_MAX_PIPES];18625 } plane[I915_MAX_PIPES];
189 int cursor_offsets[I915_MAX_PIPES];212 u8 num_sprites[I915_MAX_PIPES];213 u8 num_scalers[I915_MAX_PIPES];
1007 u32 de_irq_mask[I915_MAX_PIPES];1009 u32 pipestat_irq_mask[I915_MAX_PIPES];1099 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];1100 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];1103 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];1124 int min_cdclk[I915_MAX_PIPES];1126 u8 min_voltage_level[I915_MAX_PIPES];1186 u32 chv_dpll_md[I915_MAX_PIPES];1310 struct intel_encoder *av_enc_map[I915_MAX_PIPES];1405 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1301 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument1367 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument1384 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument1408 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument1435 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument1538 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()1623 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()3617 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()3717 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()3860 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
191 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()215 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()346 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()425 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
163 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
79 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()375 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { in intel_gvt_check_vblank_emulation()
117 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],