/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 40 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer() 42 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer() 45 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer() 46 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer() 74 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer() 114 if (!ItinData || ItinData->isEmpty()) in getHazardType() 129 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType() 130 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType() 173 if (!ItinData || ItinData->isEmpty()) in EmitInstruction() 188 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction() [all …]
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H A D | TargetInstrInfo.cpp | 1092 if (!ItinData || ItinData->isEmpty()) in getOperandLatency() 1100 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency() 1107 if (!ItinData || ItinData->isEmpty()) in getInstrLatency() 1122 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps() 1126 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps() 1156 if (!ItinData) in getInstrLatency() 1166 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency() 1273 if (!ItinData) in computeDefOperandLatency() 1274 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency() 1276 if(ItinData->isEmpty()) in computeDefOperandLatency() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 316 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 319 int getOperandLatency(const InstrItineraryData *ItinData, 323 int getOperandLatency(const InstrItineraryData *ItinData, 421 int getVLDMDefCycle(const InstrItineraryData *ItinData, 425 int getLDMDefCycle(const InstrItineraryData *ItinData, 429 int getVSTMUseCycle(const InstrItineraryData *ItinData, 433 int getSTMUseCycle(const InstrItineraryData *ItinData, 437 int getOperandLatency(const InstrItineraryData *ItinData, 443 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 452 unsigned getInstrLatency(const InstrItineraryData *ItinData, [all …]
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H A D | ARMBaseInstrInfo.cpp | 3729 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps() 3734 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps() 3737 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps() 4336 if (!ItinData || ItinData->isEmpty()) in getOperandLatency() 4438 if (!ItinData || ItinData->isEmpty()) in getOperandLatency() 4733 if (!ItinData) in getInstrLatency() 4739 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) in getInstrLatency() 4740 return getNumMicroOps(ItinData, MI); in getInstrLatency() 4743 unsigned Latency = ItinData->getStageLatency(Class); in getInstrLatency() 4760 if (!ItinData || ItinData->isEmpty()) in getInstrLatency() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | SubtargetEmitter.cpp | 82 Record *ItinData, std::string &ItinString, 87 Record *ItinData, 295 Record *ItinData, in FormItineraryStageString() argument 299 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString() 342 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString() 355 Record *ItinData, in FormItineraryBypassString() argument 358 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString() 457 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local 462 if (ItinData) in EmitStageAndOperandCycleData() 470 if (ItinData) { in EmitStageAndOperandCycleData() [all …]
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H A D | CodeGenSchedule.cpp | 1161 for (Record *ItinData : ItinRecords) { in collectProcItins() 1162 const Record *ItinDef = ItinData->getValueAsDef("TheClass"); in collectProcItins() 1169 ProcModel.ItinDefList[SC.Index] = ItinData; in collectProcItins()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument 36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()
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H A D | PPCInstrInfo.h | 311 unsigned getInstrLatency(const InstrItineraryData *ItinData, 315 int getOperandLatency(const InstrItineraryData *ItinData, 319 int getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument 322 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
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H A D | PPCInstrInfo.cpp | 136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument 139 if (!ItinData || UseOldLatencyCalc) in getInstrLatency() 140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency() 156 int Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency() 166 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument 170 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency() 192 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 1570 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 1581 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1593 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1601 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 1607 virtual int getInstrLatency(const InstrItineraryData *ItinData, 1614 int computeDefOperandLatency(const InstrItineraryData *ItinData,
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H A D | ScoreboardHazardRecognizer.h | 94 const InstrItineraryData *ItinData; variable
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 278 unsigned getInstrLatency(const InstrItineraryData *ItinData, 310 int getOperandLatency(const InstrItineraryData *ItinData, 454 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
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H A D | HexagonInstrInfo.cpp | 1882 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument 1885 return getInstrTimingClassLatency(ItinData, MI); in getInstrLatency() 4201 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument 4204 if (!ItinData) in getInstrTimingClassLatency() 4205 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency() 4209 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency() 4220 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument 4253 int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 208 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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H A D | SIInstrInfo.h | 1110 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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H A D | R600InstrInfo.cpp | 987 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
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H A D | SIInstrInfo.cpp | 7818 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
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