Searched refs:LC_LINK_WIDTH_RD_MASK (Results 1 – 11 of 11) sorted by relevance
955 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
1104 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
1511 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
372 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
2061 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
1489 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
906 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
4592 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in r600_pcie_gen2_enable()
4833 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()
1306 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes()
1575 # define LC_LINK_WIDTH_RD_MASK 0x70 macro