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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td61 foreach Lat = 3-20 in {
62 def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
63 let Latency = Lat;
68 foreach Lat = 4-16 in {
69 def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
70 let Latency = Lat;
241 foreach Lat = 3-20 in {
242 def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
243 let Latency = Lat; let NumMicroOps = 2;
268 foreach Lat = 4-16 in {
[all …]
H A DARMScheduleR52.td346 foreach Lat = 3-25 in {
347 def R52WriteILDM#Lat#Cy : SchedWriteRes<[R52UnitLd]> {
348 let Latency = Lat;
350 def R52WriteILDM#Lat#CyNo : SchedWriteRes<[]> {
351 let Latency = Lat;
546 foreach Lat = 1-32 in {
547 def R52WriteLM#Lat#Cy : SchedWriteRes<[]> {
548 let Latency = Lat;
H A DARMScheduleSwift.td382 foreach Lat = 3-25 in {
383 def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
384 let Latency = Lat;
386 def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> {
387 let Latency = Lat;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp827 unsigned Lat = 0; in adjustSchedDependency() local
831 else if (Lat) in adjustSchedDependency()
832 --Lat; in adjustSchedDependency()
834 Dep.setLatency(Lat); in adjustSchedDependency()
841 for (++I; I != E && I->isBundledWithPred() && Lat; ++I) { in adjustSchedDependency()
844 --Lat; in adjustSchedDependency()
846 Dep.setLatency(Lat); in adjustSchedDependency()
953 unsigned Lat = TSchedModel->computeInstrLatency(&MAI) - 1; in apply() local
956 dbgs() << "Need " << Lat in apply()
961 for ( ; Lat && LastSALU != E; ++LastSALU) { in apply()
[all …]
H A DSIInstrInfo.cpp7824 unsigned Lat = 0, Count = 0; in getInstrLatency() local
7827 Lat = std::max(Lat, SchedModel.computeInstrLatency(&*I)); in getInstrLatency()
7829 return Lat + Count - 1; in getInstrLatency()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ScheduleZnver3.td403 let Latency = Lat;
410 list<ProcResourceKind> ExePorts, int Lat,
413 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
417 !add(Lat, LoadLat),
429 list<ProcResourceKind> ExePorts, int Lat = 1,
431 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
437 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
443 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
451 defm : __zn3WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
460 defm : __zn3WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
[all …]
H A DX86ScheduleBdVer2.td191 list<ProcResourceKind> ExePorts, int Lat = 1,
194 let Latency = Lat;
201 list<ProcResourceKind> ExePorts, int Lat,
204 defm : PdWriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
208 !add(Lat, LoadLat),
219 list<ProcResourceKind> ExePorts, int Lat = 1,
222 defm : __pdWriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
227 list<ProcResourceKind> ExePorts, int Lat = 1,
230 defm : __pdWriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
235 list<ProcResourceKind> ExePorts, int Lat,
[all …]
H A DX86ScheduleBtVer2.td123 int Lat, list<int> Res = [], int UOps = 1,
127 let Latency = Lat;
135 let Latency = !add(Lat, 3);
143 int Lat, list<int> Res = [], int UOps = 1,
147 let Latency = Lat;
155 let Latency = !add(Lat, 5);
163 int Lat, list<int> Res = [2], int UOps = 2,
167 let Latency = Lat;
175 let Latency = !add(Lat, 5);
H A DX86ScheduleSLM.td64 int Lat, list<int> Res = [1], int UOps = 1,
68 let Latency = Lat;
76 let Latency = !add(Lat, LoadLat);
H A DX86ScheduleZnver2.td133 int Lat, list<int> Res = [], int UOps = 1,
137 let Latency = Lat;
145 let Latency = !add(Lat, LoadLat);
154 int Lat, list<int> Res = [], int UOps = 1,
158 let Latency = Lat;
166 let Latency = !add(Lat, LoadLat);
H A DX86ScheduleZnver1.td134 int Lat, list<int> Res = [], int UOps = 1,
138 let Latency = Lat;
146 let Latency = !add(Lat, LoadLat);
155 int Lat, list<int> Res = [], int UOps = 1,
159 let Latency = Lat;
167 let Latency = !add(Lat, LoadLat);
H A DX86SchedSandyBridge.td88 int Lat, list<int> Res = [1], int UOps = 1,
92 let Latency = Lat;
100 let Latency = !add(Lat, LoadLat);
H A DX86Schedule.td33 int Lat, list<int> Res, int UOps> {
35 let Latency = Lat;
H A DX86SchedBroadwell.td93 int Lat, list<int> Res = [1], int UOps = 1,
97 let Latency = Lat;
105 let Latency = !add(Lat, LoadLat);
H A DX86SchedSkylakeClient.td92 int Lat, list<int> Res = [1], int UOps = 1,
96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
H A DX86SchedHaswell.td98 int Lat, list<int> Res = [1], int UOps = 1,
102 let Latency = Lat;
110 let Latency = !add(Lat, LoadLat);
H A DX86SchedSkylakeServer.td92 int Lat, list<int> Res = [1], int UOps = 1,
96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp537 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) in changeLatency()
543 I.setLatency(Lat); in changeLatency()
549 F->setLatency(Lat); in changeLatency()
H A DHexagonSubtarget.h305 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h147 void setLatency(unsigned Lat) { in setLatency() argument
148 Latency = Lat; in setLatency()
/netbsd/external/bsd/ntp/dist/ntpd/
H A Drefclock_oncore.c3121 double Lat, Lon, Ht; in oncore_get_timestamp() local
3128 Lat = lat; in oncore_get_timestamp()
3132 Lat /= 3600000; in oncore_get_timestamp()
3137 "Ga Posn Lat = %.7f, Lon = %.7f, Ht = %.2f", Lat, in oncore_get_timestamp()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp1211 unsigned Lat = D.getLatency(); in swapAntiDependences() local
1214 Dep.setLatency(Lat); in swapAntiDependences()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td1309 (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),
/netbsd/share/misc/
H A Dairport1786 DLI:Da Lat, Vietnam
/netbsd/external/gpl3/binutils.old/dist/binutils/po/
H A Dsv.po9812 msgstr " Lat upplösare\n"

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