Searched refs:MFC1 (Results 1 – 15 of 15) sorted by relevance
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams() 956 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
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H A D | MipsSEInstrInfo.cpp | 99 Opc = Mips::MFC1; in copyPhysReg() 821 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
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H A D | MipsInstructionSelector.cpp | 657 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
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H A D | MipsScheduleP5600.td | 574 MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64,
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H A D | MipsInstrFPU.td | 558 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
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H A D | MipsFastISel.cpp | 1130 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
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H A D | MipsScheduleGeneric.td | 871 MFC1, MFC1_D64, MFHC1_D32,
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H A D | MipsSEISelLowering.cpp | 3672 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1); in emitFPROUND_PSEUDO()
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/netbsd/external/gpl3/gcc.old/dist/gcc/config/mips/ |
H A D | 74k.md | 472 ;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
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/netbsd/external/gpl3/gcc/dist/gcc/config/mips/ |
H A D | 74k.md | 472 ;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
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/netbsd/sys/external/bsd/sljit/dist/sljit_src/ |
H A D | sljitNativeMIPS_common.c | 144 #define MFC1 (HI(17)) macro 1294 return push_inst(compiler, MFC1 | flags | T(dst) | FS(TMP_FREG1), MOVABLE_INS); in sljit_emit_fop1_conv_sw_from_f64()
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/netbsd/external/gpl3/gdb/dist/sim/mips/ |
H A D | micromips.igen | 1466 010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
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H A D | ChangeLog | 2635 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
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/netbsd/external/gpl3/gdb.old/dist/sim/mips/ |
H A D | micromips.igen | 1466 010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
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H A D | ChangeLog | 2635 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
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