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Searched refs:MFLO (Results 1 – 25 of 36) sorted by relevance

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/netbsd/external/gpl3/gcc.old/dist/gcc/config/mips/
H A D4k.md89 ;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
106 ;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
114 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
H A D5k.md88 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
/netbsd/external/gpl3/gcc/dist/gcc/config/mips/
H A D4k.md89 ;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
106 ;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
114 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
H A D5k.md88 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
/netbsd/sys/external/bsd/sljit/dist/sljit_src/
H A DsljitNativeMIPS_64.c470 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
473 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
478 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
H A DsljitNativeMIPS_32.c379 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
384 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
H A DsljitNativeMIPS_common.c146 #define MFLO (HI(0) | LO(18)) macro
1033 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
1054 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
/netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/mips/
H A Dmips16-insn-e.s143 mflo.e $16 # MFLO
H A Dmips16-insn-t.s143 mflo.t $16 # MFLO
/netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/mips/
H A Dmips16-insn-e.s143 mflo.e $16 # MFLO
H A Dmips16-insn-t.s143 mflo.t $16 # MFLO
/netbsd/sys/arch/mips/
H A DREADME.models212 A multiply should not be started within two cycles of a MFHI or MFLO
213 instruction, as an interrupt that requires restarting the MFHI or MFLO
/netbsd/sys/arch/mips/mips/
H A Dbds_emul.S282 PTR_WORD bcemul_special_mfhilo # 022 MFLO
387 jr ra; mflo t0 # 022 MFLO
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
305 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
424 expandPseudoMFHiLo(MBB, MI, Mips::MFLO); in expandPostRAPseudo()
H A DMipsISelLowering.h126 MFLO, enumerator
H A DMipsSEFrameLowering.cpp821 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
H A DMipsScheduleP5600.td182 def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
H A DMipsFastISel.cpp1952 : Mips::MFLO; in selectDivRem()
/netbsd/external/gpl3/gdb/dist/binutils/testsuite/binutils-all/mips/
H A Dmips16-extend-insn.s520 extend 0x123 # MFLO
/netbsd/external/gpl3/gdb.old/dist/binutils/testsuite/binutils-all/mips/
H A Dmips16-extend-insn.s520 extend 0x123 # MFLO
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4242 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4291 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4329 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
5172 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5192 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5214 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5235 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5263 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
/netbsd/external/gpl3/gdb/dist/sim/mips/
H A Dm16.igen985 11101,3.RX,000,10010:RR:16::MFLO
H A DChangeLog616 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
634 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
636 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
779 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
/netbsd/external/gpl3/gdb.old/dist/sim/mips/
H A Dm16.igen985 11101,3.RX,000,10010:RR:16::MFLO
H A DChangeLog616 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
634 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
636 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
779 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,

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