| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1147 MSTORE, enumerator
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| H A D | SelectionDAGNodes.h | 1349 case ISD::MSTORE:
1385 N->getOpcode() == ISD::MSTORE ||
2347 N->getOpcode() == ISD::MSTORE;
2388 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2410 return N->getOpcode() == ISD::MSTORE;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 115 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
170 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
218 setOperationAction(ISD::MSTORE, BoolW, Custom); in initializeHVXLowering()
1711 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
1843 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
1866 if (MemOpc == ISD::MSTORE) { in SplitHvxMemOp()
2069 case ISD::MSTORE: in LowerHvxOperation()
2122 case ISD::MSTORE: return LowerHvxMaskedOp(Op, DAG); in LowerHvxOperation()
2174 case ISD::MSTORE: in LowerHvxOperationWrapper()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 388 case ISD::MSTORE: return "masked_store"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 2169 case ISD::MSTORE: in SplitVectorOperand()
4531 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break; in WidenVectorOperand()
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| H A D | SelectionDAG.cpp | 692 case ISD::MSTORE: { in AddNodeIDCustom()
7596 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
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| H A D | LegalizeDAG.cpp | 1161 case ISD::MSTORE: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 1508 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N), in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 1721 case ISD::MSTORE: return visitMSTORE(N); in visit()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 516 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
577 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
677 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
756 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
2335 case ISD::MSTORE: in LowerOperation()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 648 def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1443 case ISD::MSTORE: in SelectT2AddrModeImm7Offset()
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| H A D | ARMISelLowering.cpp | 275 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
340 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1199 setOperationAction(ISD::MSTORE, VT, Custom); in AArch64TargetLowering()
1490 setOperationAction(ISD::MSTORE, VT, Custom); in addTypeForFixedLengthSVE()
4632 case ISD::MSTORE: in LowerOperation()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1403 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1583 setOperationAction(ISD::MSTORE, VT, Custom); in X86TargetLowering()
1737 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1744 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1890 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2032 setTargetDAGCombine(ISD::MSTORE); in X86TargetLowering()
30390 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG); in LowerOperation()
50831 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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